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st ST2202A 8 bit integrated microcontroller with 256k bytes ro m notice:sitronixtechnologycorp.reservestherigh ttochangethecontentsinthisdocumentwithoutp riornotice.thisisnotafinalspecification. someparametersaresubjecttochange. ver2.5 1/75 9/16/2008 1 1 . . f f e e a a t t u u r r e e s s totally static 8-bit cpu rom: 256k x 8-bit ram: 4k x 8-bit stack: up to 128-level deep operation voltage: 2.4v ~ 5.5v operation frequency: C3.0mhzmin.2.4v C4.0mhzmin2.7v low voltage detector (lvd) memory interface to rom, ram, flash memory configuration Cthreekindsofbankforprogram,dataandinterru pts C12bitbankregistersupportsupto44mbytes C6programmablechipselectswith4modes Cmaximumsingledeviceof16mbytesat cs5 general-purpose i/o (gpio) ports C48multiplexedcmosbidirectionalbitprogrammabl e i/os Chardwaredebounceoptionforporta Cbitprogrammablepullupforinputpins Cbitprogrammablepullup/downandopendrain/cmos forportc programmable watchdog timer (wdt) timer/counter Ctwo8bittimer,onecanbea16biteventcounte r Cone8bitbasetimerwith5coexistentinterrupt time settings three clocking outputs Cclocksourcesincludingtimer0/1,baudrategener ator 11 prioritized interrupts with dedicated exception vectors Cexternalinterrupt(edgetriggered) Ctimer0interrupt Ctimer1interrupt Cbasetimerinterrupt Cportainterrupt(transitiontriggered) Cdacreloadinterrupt Clcdframeinterrupt Cspiinterrupts(x2) Cuartinterrupts(x2) dual clock sources with warm-up timer Clowfrequencycrystaloscillator(oscx) 32768hz Crcoscillator(osc) 500k~4mhz Chighfrequencycrystal/resonatoroscillator (bondingoption) 455k~4mhz direct memory access (dma) Cblocktoblocktransfer Cblocktosingleport lcd controller (lcdc) Csoftwareprogrammablescreensizeupto240x120 (including160x160,160x80,etc.) Csupport1,4bitlcddatabus Csharesystemmemorywithdisplaymemory Cuniqueinternalbusformemorysharingwithnolo ssof thecputime Cdiversefunctionsincludingvirtualscreen,pann ing, scrolling,contrastcontrolandalternatingsignal generator Csupportsoftware16graylevels universal asynchronous receiver/transmitter (uart) Cfullduplexoperation Cbaudrategeneratorwithonedigitalpll Cstandardbaudratesof600bpsto115.2kbps Cdirectgluelesssupportofirdaphysicallayerpr otocol Ctwosetsofi/os(tx,rx)fortwoindependentdevi ces serial peripheral interface (spi) Cmasterandslavemodes C5serialsignalsincludingenableanddataready Conestagebufferfortransmitterandreceiverfor continuousdataexchange Cprogrammabledatalengthfrom7bitto16bit programmable sound generator (psg) Ctwochannelswiththreeplayingmodes Ctone/noisegenerator C16levelvolumecontrol C8bitpwmdacforspeech/voice Ctwodedicatedoutputsfordirectlydrivingandla rge current three power down modes Cwai0mode Cwai1mode Cstpmode
ST2202A ver2.5 2 / 75 9/16/2008 2 2 . . g g e e n n e e r r a a l l d d e e s s c c r r i i p p t t i i o o n n thest2202isa8bitintegratedmicrocontrollerde signedwith cmossilicongatetechnology.thetruestaticcpuc ore,power downmodesanddualoscillatorsdesignmakesthest 2202 suitableforpowersavingandlongbatterylifedes igns.the st2202integratesvariouslogictosupportfunction sonchip whichareneededbysystemdesigners.thisisalso important forlowersystemcomplexity,smallboardsizeand, ofcourse, shortertimetomarketandlesscost. thest2202featuresthecapacityofmemoryaccesso f maximum44mbyteswhichisneededbyproductswith large databases,andalsodmafunctionforfastmemoryt ransfer. sixchipselectsareequippedfordirectconnection toexternal rom,sram,flashmemoryorotherdevices.maximumo ne singledeviceof16mbytesispossible. thest2202has48i/osgroupedinto6ports,porta ~porte andportl.eachpincanbeprogrammedtoinputor output. therearetwooptions:pullup/downforinputsofp ortcand onlypullupforinputsoftheotherports.incase ofoutput, thereareopendrain/cmosoptionsforoutputsofpo rtcand onlycmosfortheotherports.porta/bisdesigned for keyboardscanwithdebounceandtransitiontrigger edinterrupt atporta,whileportc/d/e/laresharedwithother system functions.allthepropertiesofi/opinsarestill programmable whentheyareassignedtoanotherfunction.thisen largesthe flexibilityoftheusageoffunctionsignals. theabilityofdrivinglargelcdpanels,upto240x 120,and software16graylevelsupportmayrichthedisplay information andthediversityofcontentsaswell.thisisdone withnoneed ofexternaldisplayrambecauseoftheinternalmem ory sharingdesign. thest2202equipsserialcommunicationportsofone uart andonespitoperformdifferentcommunications,ex .:rs232 andirda,withsystemcomponentsorotherproducts suchas pc,notebook,andpopularpda.threeclockingoutpu tscan producesynthesizedpwmsignalsorhighfrequencyc arrierfor irremotecontrol.thishelpsproductsbecomemore usefulin ourdailylife. thebuiltintwochannelpsg/onechannelpwmdacar efor theproductionofkeytone,melody,voice,andspee ch.two dedicatedpinscandriveabuzzerdirectlyformini mumcost. withtheseintegratedfunctionsinside,thest2202 singlechip microcontrollerisarightsolutionforpda,transl ator,databank andotherconsumerproducts. clock generator osc clock generator oscx osci oscxi oscxo xio vcc gnd poweron reset reset a[22:0] d[7:0] 8bit external memory bus rd wr psg/ pwmdac psgo/psgob 8bitstatic cpu rom 256kbytes baudrate generator dma basetimer 8bit sram 4kbytes wdt interrupt controller bank control logic pa7~0 porta debounce logic transition detector pb7~0 portb uartwith irdamode spi intx/pc0 portc sck/pc1 sdi/pc2 sdo/pc3 txd0/pc6 portc rxd0/pc7 portc test1/2 chipselect logic mmd/cs0 portd timer0/1 8bit clocking output porte tco0/pe0 pe7~2 porte lcd controller portl ld[3:0]/pl3~0 cp/pl4 ac/pl5 load/pl6 flm/pl7 txd1/pd6 rxd1/pd7 portd /pc5 data_ready /pc4 ss 0 ~ /pd4 1 ~ cs5 /pd5 /a23 cs6 poff blank tco1/pe1 bco/pe2 pvcc/pgnd xmd figure 2-1 st2202 block diagram
ST2202A ver2.5 3 / 75 9/16/2008 3 3 . . s s i i g g n n a a l l d d e e s s c c r r i i p p t t i i o o n n s s table 3-1 signal function groups function group pad no. designation description power 17,52, 90 vcc,pvcc vcc: powersupplyforsystem pvcc: powersupplyforpsgoandpsgob ground 22,48, 49,71 gnd,pgnd gnd: systempowerground pgnd: powergroundforpsgoandpsgob systemcontrol 15, 1,77, 26 reset ,test1/2 mmd/ cs0 reset : activelowsystemresetsignalinput test1/2: leavethemopenwhennormaloperation mmd/cs0: memorymodesselectionpin normal mode: enableinternalrom. mmd/ cs0 connectstognd. emulation mode: disableinternalrom. mmd/ cs0 connectstochipselectpinofexternalrom. oneresistorshouldbeaddedbetweenvccandthisp in. afterresetcycles,mmd/ cs0 changestobeanoutput,and outputssignal cs0 . clock 16, 18~21 oscxo,oscxi,osci, xio,xmd xmd: highfrequencyoscillator(osc)modeselectioninp ut low: crystalmode.onecrystalorresonatorshouldbe connectedbetweenosciandxio high: resistoroscillatormode.oneresistorshouldbe connectedbetweenosciandvcc oscxi, oscxo: connectone32768hzcrystalbetweenthese twopinswhenusinglowfrequencyoscillator 69,70 wr , rd externalmemoryr/wcontrolsignals 2~4, 81~89, 91~101 a[22:0] externalmemoryaddressbus externalmemory bussignals 72~76, 78~80 d[7:0] externalmemorydatabus psg/pwmdac 50,51 psgo,psgob psgoutputs.connect toonebuzzerorspeaker keyboardscan signal(returnline) 23~25, 27~31 pa7~0 i/oporta gpio 32~39 pb7~0 i/oportb chipselects 61~66 cs6 /a23/pd5, 1 ~ cs5 /pd4~0 i/oportdandchipselectoutputs uart 46,47, 67,68 rxd0/pc7, txd0/pc6, rxd1/pd7,txd1/pd6 uartsignalsandi/os spi 41~45 data_ready /pc5, ss /pc4,sdo/pc3, sdi/pc2,sck/pc1 spisignalsandi/os
ST2202A ver2.5 4 / 75 9/16/2008 table 3-2 signal function groups (continued) function group pad no. designation description externalinterrupt 40 intx/pc0 externalinterrupti nputs clockingoutput 53~55 bco/pe2,tco1/pe1, tco0/pe0 clockingoutputs gpio 56~60 pe7~3 i/oporte lcdcontroller 5~14 flm/pl7,load/pl6, ac/pl5,cp/pl4, ld[3:0]/pl3~0, poff , blank lcdcontrolsignals
ST2202A ver2.5 5 / 75 9/16/2008 4 4 . . p p a a d d d d i i a a g g r r a a m m
ST2202A ver2.5 6 / 75 9/16/2008 5 5 . . d d e e v v i i c c e e i i n n f f o o r r m m a a t t i i o o n n 1. pad size: 90um x 90um 2. substrate: gnd 3. chip size: 3160um x 3210um pad no. symbol x y 1 test1 1445 1510 2 a14 1320 1510 3 a15 1195 1510 4 a16 1085 1510 5 pl0 975 1510 6 pl1 865 1510 7 pl2 755 1510 8 pl3 645 1510 9 pl4 535 1510 10 pl5 425 1510 11 pl6 315 1510 12 pl7 205 1510 13 blank 95 1510 14 poff 15 1510 15 reset 125 1510 16 xmd 235 1510 17 vcc 345 1510 18 xio 455 1510 19 osci 565 1510 20 oscxo 675 1510 21 oscxi 785 1510 22 gnd 895 1510 23 pa0 1005 1510 24 pa1 1130 1510 25 pa2 1255 1510 26 mmd 1485 1489 27 pa3 1485 1354 28 pa4 1485 1229 29 pa5 1485 1119 30 pa6 1485 1009 31 pa7 1485 899 32 pb0 1485 789 33 pb1 1485 679 34 pb2 1485 569 pad no. symbol x y 35 pb3 1485 459 36 pb4 1485 349 37 pb5 1485 239 38 pb6 1485 129 39 pb7 1485 19 40 pc0 1485 91 41 pc1 1485 201 42 pc2 1485 311 43 pc3 1485 421 44 pc4 1485 531 45 pc5 1485 641 46 pc6 1485 751 47 pc7 1485 861 48 gnd 1485 971 49 pgnd 1485 1135 50 psgo 1485 1260 51 psgob 1485 1385 52 pvcc 1485 1510 53 pe0 1243.4 1510 54 pe1 1118.4 1510 55 pe2 993.4 1510 56 pe3 883.4 1510 57 pe4 773.4 1510 58 pe5 663.4 1510 59 pe6 553.4 1510 60 pe7 443.4 1510 61 pd0 333.4 1510 62 pd1 223.4 1510 63 pd2 113.4 1510 64 pd3 3.4 1510 65 pd4 106.6 1510 66 pd5 216.6 1510 67 pd6 326.6 1510 68 pd7 436.6 1510 pad no. symbol x y 69 wr 546.6 1510 70 rd 656.6 1510 71 gnd 766.6 1510 72 d7 876.6 1510 73 d6 986.6 1510 74 d5 1096.6 1510 75 d4 1206.6 1510 76 d3 1331.6 1510 77 test2 1456.6 1510 78 d2 1485 1294.9 79 d1 1485 1169.9 80 d0 1485 1044.9 81 a0 1485 934.9 82 a1 1485 824.9 83 a2 1485 714.9 84 a3 1485 604.9 85 a4 1485 494.9 86 a5 1485 384.9 87 a6 1485 274.9 88 a7 1485 164.9 89 a17 1485 54.9 90 vcc 1485 55.1 91 a18 1485 165.1 92 a19 1485 275.1 93 a20 1485 385.1 94 a21 1485 495.1 95 a22 1485 605.1 96 a8 1485 715.1 97 a9 1485 825.1 98 a10 1485 935.1 99 a11 1485 1045.1 100 a12 1485 1170.1 101 a13 1485 1295.1
ST2202A ver2.5 7 / 75 9/16/2008 6 6 . . c c p p u u register model 7 0 a 7 0 y 7 0 x 7 0 pch pcl 7 0 1 s accumulatora indexregistery indexregisterx programcounterpc stackpointers accumulator (a) theaccumulatorisageneralpurpose8bitregister thatstores theresultsofmostarithmeticandlogicoperations .inaddition, theaccumulatorusuallycontainsoneofthetwodat awords usedintheseoperations. index registers (x,y) therearetwo8bitindexregisters( x and y ),whichmaybe usedtocountprogramstepsortoprovideandindex valueto beusedingeneratinganeffectiveaddress.whenex ecutingan instruction,whichspecifiesindexedaddressing,th ecpu fetchestheopcodeandthebaseaddress,andmodif iesthe addressbyaddingtheindexregistertoitpriorto performing thedesiredoperation.preorpostindexingofindi rect addressesispossible. stack pointer (s) thestackpointerisan8bitregister,whichisus edtocontrol theaddressingofthevariablelengthstack.itsr angefrom 100hto1ffhtotalfor256bytes(128leveldeep). thestack pointerisautomaticallyincrementanddecrementun dercontrol ofthemicroprocessortoperformstackmanipulation sunder directionofeithertheprogramorinterrupts(irq) .thestack allowssimpleimplementationofnestedsubroutines and multiplelevelinterrupts.thestackpointerisini tializedbythe userssoftware. program counter (pc) the16bitprogramcounterregisterprovidesthead dress, whichstepthemicroprocessorthroughsequentialpr ogram instructions.eachtimethemicroprocessorfetches and instructionfromprogrammemory,thelowerbyteof the programcounter( pcl )isplacedontheloworderbitsofthe addressbusandthehigherbyteoftheprogramcoun ter( pch ) isplacedonthehighorder8bits.thecounteris increment eachtimeaninstructionordataisfetchedfrompr ogram memory. status register (p) the8bitprocessorstatusregistercontainsseven statusflags. someoftheseflagsarecontrolledbyprogram;othe rsmaybe alsocontrolledbythecpuaswell.theinstruction setcontains amemberofconditionalbranchinstructionsthatar edesigned toallowtestingoftheseflags.referto table61 table 6-1 status register (p) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 n v 1 b d i z c bit7: n : signedflagbyarithmetic 1=negative 0=positive bit3: d : decimalmodeflag 1=decimalmode 0=binarymode bit6: v : overflowofsignedarithmeticflag 1=negative 0=positive bit2: i : interruptdisableflag 1=interruptdisable 0=interruptenable bit1: z : zeroflag 1=zero 0=nonzero bit4: b : brk interruptflag 1= brk interruptoccur 0=non brk interruptoccur bit0: c : carryflag 1=carry 0=noncarry
ST2202A ver2.5 8 / 75 9/16/2008 7 7 . . m m e e m m o o r r y y c c o o n n f f i i g g u u r r a a t t i i o o n n 7.1 memory map thelogicalmemoryspaceofst2202isdividedinto 3parts: $0000~$0fff(4k),$4000~$7fff(16k),and$8000~ffff (32k).firstisforcontrolregisters,stackandsy stemmemory. secondandthirdarebankedareas.logicaladdress inthese twoareascombinestwobankregisters, prr and drr respectively,andthenbemappedtoaphysicaladdr ess. prr istheprogramrombankregisterandis12bitlong ,while drr isthedatarombankregisterofthelengthof11 bits. bothcanrefertoamaximumspaceof64mbytes. only44m(28mwhen csm0 =0)bytesis addressablebychipselects. referto figure71formemorymappingofst2202. . controlregister zeropage usermemory 0000 007f 0080 00ff usermemory/ displaymemory 0100 0200 01ff 3fff 4000 programmemory (prr) 16kbytes 7fff 8000 datamemory (drr) 32kbytes ffff 0000000~ 0003fff 0004000~ 0007fff drr=000h prr=001h prr=000h 0008000~ 000bfff 000c000~ 000ffff drr=001h prr=003h prr=002h 3ff0000~ 3ff3fff 3ff4000~ 3ff7fff drr=7feh prr=ffdh prr=ffch 3ff8000~ 3ffbfff 3ffc000~ 3ffffff drr=7ffh prr=fffh prr=ffeh interruptvector 7fe2 cpumemorymapping physicalmemorymapping 64mbytes stack reserved 0fff 1000 figure 7-1 memory mapping
ST2202A ver2.5 9 / 75 9/16/2008 7.2 control registers address$000~$07fisforcontrolregisters.refert o table71forsummaryofallregisters.therearem oredetailsofregistersin therelatedsections. table 7-1 control registers summary address name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default $000 pa* r/w pa[7] pa[6] pa[5] pa[4] pa[3] pa[2] pa[1] pa[0] 11111111 $001 pb* r/w pb[7] pb[6] pb[5] pb[4] pb[3] pb[2] pb[1] pb[0] 11111111 $002 pc* r/w pc[7] pc[6] pc[5] pc[4] pc[3] pc[2] pc[1] pc[0] 11111111 $003 pd* r/w pd[7] pd[6] pd[5] pd[4] pd[3] pd[2] pd[1] pd[0] 11111111 $004 pe* r/w pe[7] pe[6] pe[5] pe[4] pe[3] pe[2] pe[1] pe[0] 11111111 $005 psc r/w psc[7] psc[6] psc[5] psc[4] psc[3] psc[2] psc[1 ] psc[0] 11111111 $008 pca r/w pca[7] pca[6] pca[5] pca[4] pca[3] pca[2] pca[1 ] pca[0] 00000000 $009 pcb r/w pcb[7] pcb[6] pcb[5] pcb[4] pcb[3] pcb[2] pcb[1 ] pcb[0] 00000000 $00a pcc r/w pcc[7] pcc[6] pcc[5] pcc[4] pcc[3] pcc[2] pcc[1 ] pcc[0] 00000000 $00b pcd r/w pcd[7] pcd[6] pcd[5] pcd[4] pcd[3] pcd[2] pcd[1 ] pcd[0] 00000000 $00c pce r/w pce[7] pce[6] pce[5] pce[4] pce[3] pce[2] pce[1 ] pce[0] 00000000 $00d pfc r/w rxd0 txd0 srdy ss mosi miso sck intx 00000000 $00e pfd r/w rxd1 txd1 cs6 cs5 cs4 cs3 cs2 cs1 00000000 $00f pmcr r/w pull pdbn integ csm1 csm0 bco tco1 tco0 10000 00 $010 psg0l r/w psg0[7] psg0[6] psg0[5] psg0[4] psg0[3] psg0[2] psg0[1] psg0[0] 00000000 $011 psg0h r/w psg0[11] psg0[10] psg0[9] psg0[8] 0000 $012 psg1l r/w psg1[7] psg1[6] psg1[5] psg1[4] psg1[3] psg1[2] psg1[1] psg1[0] 00000000 $013 psg1h r/w psg1[11] psg1[10] psg1[9] psg1[8] 0000 $014 dac r/w dac[7] dac[6] dac[5] dac[4] dac[3] dac[2] dac[1 ] dac[0] 00000000 r/w pck[2] pck[1] pck[0] prbs c1en c0en dace=0 0000000 $016 psgc r/w pck[2] pck[1] pck[0] dmd[1] dmd[0] inh dace=1 0000000 $017 vol r/w vol1[3] vol1[2] vol1[1] vol1[0] vol0[3] vol0[2] vol0[1] vol0[0] 00000000 $020 bten r/w bten[4] bten[3] bten[2] bten[1] bten[0] 00000 r btsr[4] btsr[3] btsr[2] btsr[1] btsr[0] 00000 $021 btsr* w btclr 0 r prs[7] prs[6] prs[5] prs[4] prs[3] prs[2] prs[1] prs[0] 00000000 $023 prs* w sres sena sent 000 $024 t0m r/w t0m[5] t0m[4] t0m[2] t0m[1] t0m[0] 00000 $025 t0c r/w t0c[7] t0c[6] t0c[5] t0c[4] t0c[3] t0c[2] t0c[1 ] t0c[0] 00000000 $026 t1m r/w t1m[4] t1m[3] t1m[2] t1m[1] t1m[0] 00000 $027 t1c r/w t1c[7] t1c[6] t1c[5] t1c[4] t1c[3] t1c[2] t1c[1 ] t1c[0] 00000000 $028 dmsl* w dms[7] dms[6] dms[5] dms[4] dms[3] dms[2] dms[1] dms[0] ???????? $029 dmsh* w dms[15] dms[14] dms[13] dms[12] dms[11] dms[10] dms[9] dms[8] ???????? $02a dmdl* w dmd[7] dmd[6] dmd[5] dmd[4] dmd[3] dmd[2] dmd[1] dmd[0] ???????? $02b dmdh* w dmd[15] dmd[14] dmd[13] dmd[12] dmd[11] dmd[10] dmd[9] dmd[8] ???????? $02c dcntl* w dcnt[7] dcnt[6] dcnt[5] dcnt[4] dcnt[3] dcnt[2] dcnt[1] dcnt[0] ???????? $02d dcnth* w dmam dcnt[11] dcnt[10] dcnt[9] dcnt[8] ????? r xsel ostp xstp wskp wait irren high 00000001 $030 sys* w xsel ostp xstp wskp wait irren lvden 00000000 $031 irr r/w irr[7] irr[6] irr[5] irr[4] irr[3] irr[2] irr[1 ] irr[0] 00000000 $032 prrl r/w prr[7] prr[6] prr[5] prr[4] prr[3] prr[2] prr[1 ] prr[0] 00000000 $033 prrh r/w prr[11] prr[10] prr[9] prr[8] 0000 $034 drrl r/w drr[7] drr[6] drr[5] drr[4] drr[3] drr[2] drr[1] drr[0] 00000000 $035 drrh r/w drr[10] drr[9] drr[8] 000 $036 dmrl r/w dmr[7] dmr[6] dmr[5] dmr[4] dmr[3] dmr[2] dmr[1] dmr[0] 00000000 $037 dmrh r/w dmr[10] dmr[9] dmr[8] 000 r/w wdten wdtps test test 0000 $038 misc w resetwdt $03c ireql r/w irlcd irbt irpt irt1 irt0 irdac irx 0000000 $03d ireqh r/w irurx irutx irsrx irstx 0000 $03e ienal r/w ielcd iebt iept iet1 iet0 iedac iex 0000000 $03f ienah r/w ieurx ieutx iesrx iestx 0000
ST2202A ver2.5 10 / 75 9/16/2008 $040 lssal* w ssa[7] ssa[6] ssa[5] ssa[4] ssa[3] ssa[2] ssa[1] ssa[0] 00000000 $041 lssah* w ssa[15] ssa[14] ssa[13] ssa[12] ssa[11] ssa[10] ssa[9] ssa[8] 00000000 $042 lvpw* w vp[7] vp[6] vp[5] vp[4] vp[3] vp[2] vp[1] vp[0] 0 0000000 $043 lxmax r/w xm[7] xm[6] xm[5] xm[4] xm[3] xm[2] xm[1] xm[0] 00000000 $044 lymax r/w ym[7] ym[6] ym[5] ym[4] ym[3] ym[2] ym[1] ym[0] 00000000 $045 lpan r/w pan[2] pan[1] pan[0] 000 $047 lctr r/w lpwr blnk rev 100 $048 lckr* w lmod lck[3] lck[2] lck[1] lck[0] 00000 $049 lfra* w fra[5] fra[4] fra[3] fra[2] fra[1] fra[0] 00 0000 $04a lac r/w ac[4] ac[3] ac[2] ac[1] ac[0] 00000 $04b lpwm r/w lpwm[5] lpwm[4] lpwm[3] lpwm[2] lpwm[1] lpwm[0] 000000 $04c pl* r/w pl[7] pl[6] pl[5] pl[4] pl[3] pl[2] pl[1] pl[0] 11111111 $04e pcl* w pcl[7] pcl[6] pcl[5] pcl[4] pcl[3] pcl[2] pcl[1] pcl[0] 00000000 $050 sdat0al r/w sd[7] sd[6] sd[5] sd[4] sd[3] sd[2] sd[1] sd[0] ???????? $051 sdatah r/w sd[15] sd[14] sd[13] sd[12] sd[11] sd[10] sd[9] sd[8] ???????? $052 sctr r/w spien rxien erien meren drinv pol pha smod 00000000 $053 sckr r/w sck[2] sck[1] sck[0] bc[3] bc[2] bc[1] bc[0] 000 0000 r rxrdy txemp sbz mderr oerr bcerr 000000 $054 ssr* w writeanyvaluetoclearssr $060 uctr r/w pen pmod umod brk 0000 r fer per oer rxbz rxen txbz txen 0000000 $061 ustr* w rxtrg rxen txtrg txen 0000 $062 irctr r/w rxinv txinv pw1 pw0 iren 00000 $063 bctr r/w test bstr bmod bgren 0000 $064 udata r/w ud[7] ud[6] ud[5] ud[4] ud[3] ud[2] ud[1] ud[0] ???????? $066 brs r/w brs[7] brs[6] brs[5] brs[4] brs[3] brs[2] brs[1 ] brs[0] ???????? $067 bdiv r/w bdiv[7] bdiv[6] bdiv[5] bdiv[4] bdiv[3] bdiv[2] bdiv[1] bdiv[0] ???????? note: 1.undefinedbytesandbitsshouldnotbeus ed,pleasekeepit0. * do not use read-modify-write instructions, rmbx and smbx, to write-only registers. 7.3 bank registers therearefourkindsofbankregisters,interruptb ankregister ( irr ),programrombankregister( prr ),datarombank register( drr ),anddmasourcedatabankregister( dmr ). irr , prr refertologicaddressrangeof$4000~$7fff,while drr , dmr refertotherangeof$8000~$ffff.theregister length,addressablerange,andsizearelistedin table72. whennormalprocessisrunning,addressfallsinon eofthe twoareaswillactivateeither prr or drr . inthecaseofinterrupts,bit[11:8]of prr willbemaskedto zeroandbit[7:0]willbereplacedby irr .thisreplacement lastsuntilinstructionrtiismet.thatis,thein terruptvectors andserviceroutineswillallbaseon irr .operationof irr is alsoenabledby irren of sys . althoughamaximumnumberof64mbytescanbeaddre ssed, thephysicalsizeislowerthanthatbecauseofthe limitofchip selects.pleaserefertosection 10formoredetails. table 7-2 bank registers and addressable range address name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 addressabl e range size $031 irr r/w irr[7] irr[6] irr[5] irr[4] irr[3] irr[2] irr[1] irr[0] $0000000~ $03fffff 4m $032 prrl r/w prr[7] prr[6] prr[5] prr[4] prr[3] prr[2] prr[1] prr[0] $033 prrh r/w prr[11] prr[10] prr[9] prr[8] $0000000~ $3ffffff 64m* $034 drrl r/w drr[7] drr[6] drr[5] drr[4] drr[3] drr[2] drr[1] drr[0] $035 drrh r/w drr[10] drr[9] drr[8] $0000000~ $3ffffff 64m* $036 dmrl r/w dmr[7] dmr[6] dmr[5] dmr[4] dmr[3] dmr[2] dmr[1] dmr[0] $037 dmrh r/w dmr[10] dmr[9] dmr[8] $0000000~ $3ffffff 64m* note:*pleaserefertosection 10forthelimitofaddressablesize. table 7-3 system control register sys address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default r xsel ostp xstp wskp wait irren high 00000001 $030 sys w xsel ostp xstp wskp wait irren lvden 00000000 bit1: irren :enable/disablebankregisterirr 0 =disableirr 1=enableirr
ST2202A ver2.5 11 / 75 9/16/2008 7.4 ram internalstaticramcanbedividedinto3partsin function.first isthezeropagememory,secondisforstack,andt hirdcanbe usedaslcdframebufferorforgeneralpurpose. zero page data ram ($0080~$00ff) total128bytesofdataraminzeropageisveryus efulfor programmers.theyprovideshortinstructioncodesa ndcycles. usezeropageaddressingmodeonthevariablesint hisarea usuallyspeedsuptheoverallperformance. stack ram ($0100~$01ff) thest2202has256bytesstackfrom$0100to$01ff. it providesamaximumof128levelsforsubroutines.b ysetting stackpointercarefully,stackmemorycanalsobeu sedasdata memory. user memory and lcd frame buffer ($0200~$0fff) thest2202sharesmemoryforbothusermemoryandl cd framebuffer.therangeoflcdframebufferwillbe fixedafter initializationoflcdcontrolregisters.memorybey ondisuser memory.readandwriteoperationscanbeappliedto lcd framebuffertomaintaindisplaycontent,andalmos tnoneof thecputimeisaffected.thisiscontributedbyon especial memorytransfertechniqueofdisplaydatafromlcd frame buffertothelcdcontroller.
ST2202A ver2.5 12 / 75 9/16/2008 8 8 . . i i n n t t e e r r r r u u p p t t c c o o n n t t r r o o l l l l e e r r thest2202supports11hardwareinternal/externali nterrupts aswellasonesoftwareinterruptbrk.thereare12 exception vectorsfortheseinterruptsandanotheroneforre set.all interruptsarecontrolledbyinterruptdisableflag i (bit2of statusregister p ),andinitiateif i equals0.hardware interruptsarefurthercontrolledbyinterruptenab leregister iena .settingbitsof iena enablesrespectiveinterrupts. theinterruptcontrollerownsonepriorityarbitrat or.whenmore thanoneinterruptshappenatthesametime,theon ewith lowerprioritynumberwillbeexecutedfirst.refer to table81 forprioritiesofinterrupts. onceaninterrupteventwasenabledandthenhappen s,the cpuwakesup(ifineitherwaitmode),andassociat edbitof interruptrequestregister( ireq )willbeset.if i flagiscleared, therelatedvectorwillbefetchedandthentheint erruptservice routine(isr)willbeexecuted.interruptrequestf lagcanbe clearedbytwomethods.oneistowrite0to ireq ,theother istoinitiaterelatedinterruptserviceroutine.h ardwarewill automaticallycleartheinterruptrequestflag.all interrupt vectorsarelistedin table81. table 8-1 interrupt vectors name signal source vector address priority description brk internal $7fff,$7ffe 1 softwarebrkoperationv ector reset external $7ffd,$7ffc 0 resetvector $7ffb,$7ffa reserved intx external $7ff9,$7ff8 6 pc0edgeinterrupt dac internal $7ff7,$7ff6 7 reloaddacdatainterrup t t0 internal/external $7ff5,$7ff4 8 timer0interrupt t1 internal/external $7ff3,$7ff2 9 timer1interrupt pt external $7ff1,$7ff0 10 portatransitioninterr upt bt internal $7fef,$7fee 11 basetimerinterrupt lcd internal $7fed,$7fec 12 lcdframeinterrupt $7feb,$7fea reserved stx external $7fe9,$7fe8 2 spitransmitbufferempt yinterrupt srx external $7fe7,$7fe6 3 spireceivebufferready interrupt utx external $7fe5,$7fe4 4 uartreceiverinterrupt urx external $7fe3,$7fe2 5 uarttransmitterinterru pt table 8-2 interrupt request register (ireq) address name r/w bit 7/15 bit 6/14 bit 5/13 bit 4/12 bit 3/11 bit 2/10 bit 1/9 bit 0/8 default $03c ireql r/w irlcd irbt irpt irt1 irt0 irdac irx 0000000 $03d ireqh r/w irurx irutx irsrx irstx 0000 bit0: irx: intxinterruptrequestbit 1=intxedgeinterruptoccurs 0 =intxedgeinterruptdoesntoccur bit1: irdac: dacreloadinterruptrequestbit 1=dactimeoutinterruptoccurs 0 =dactimeoutinterruptdoesntoccur bit2: irt0: timer0interruptrequestbit 1=timer0overflowinterruptoccurs 0 =timer0overflowinterruptdoesntoccur bit3: irt1: timer1interruptrequestbit 1=timer1overflowinterruptoccurs 0 =timer1overflowinterruptdoesntoccur bit4: irpt: portainterruptrequestbit 1=portatransitioninterruptoccurs 0 =portatransitioninterruptdoesntoccur bit5: irbt: basetimerinterruptrequestbit 1=timebaseinterruptoccurs 0 =timebaseinterruptdoesntoccur bit6: irlcd: lcdframeinterruptrequestbit 1=lcdframeinterruptoccurs 0 =lcdframeinterruptdoesntoccur bit8: irstx: spitransmitterinterruptrequestbit 1=spitransmitbufferisempty 0 =spitransmitbufferisoccupied bit9: irsrx: spireceiverinterruptrequestbit 1=spireceivebufferisready 0 =spireceivebufferisnotready bit10: irutx: uarttransmitterinterruptrequestbit 1=uartdatatransmissioncompletes 0 =uartdatatransmissionnotcompletes
ST2202A ver2.5 13 / 75 9/16/2008 bit11: irurx: uartreceiverinterruptrequestbit 1=uartdatareceivingcompletes 0 =uartdatareceivingnotcompletes table 8-3 interrupt enable register (iena) address name r/w bit 7/15 bit 6/14 bit 5/13 bit 4/12 bit 3/11 bit 2/10 bit 1/9 bit 0/8 default $03e ienal r/w ielcd iebt iept iet1 iet0 iedac iex 0000000 $03f ienah r/w ieurx ieutx iesrx iestx 0000 bitx: 1=enablerespectiveinterrupt 0=disablerespectiveinterrupt 8.1 interrupt description brk instructionbrkwillcausesoftwareinterruptwhe ninterrupt disableflag( i )iscleared.hardwarewillpush pc , p registers tostackandthensetsinterruptdisableflag( i ) .program counterwillbeloadedwiththebrkvectorfromloc ations $7ffeand$7fff . reset apositivetransitionof reset pinwillmakeaninitialization sequencetobegin.afterthesystemhasbeenoperat ing,one lowlevelsignalonthislineofatleasttwoclock cycleswill ceaseST2202Activity.whenapositiveedgeisdete cted,there isaninitializationsequencelastingsixclock cycles.thenthe interruptdisableflagisset ,thedecimalmodeiscleared and theprogramcounterwillbeloadedwiththeresetv ectorfrom locations$7ffc(lowbyte)and$7ffd(highbyte) .thisisthe startlocationforprogramflow.thisinputshould behighin normaloperation. intx interrupt the irx (intxinterruptrequest)flagwillbesetwhilein tx edgesignaloccurs.theintxinterruptwillbeacti vewheniex (intxinterruptenable)isset,andinterruptdisab leflagis cleared.hardwarewillpushpc,pregistersto stackand setsinterruptdisableflag( i ) .programcounterwillbeloaded withtheintxvectorfromlocations$7ff8and$7ff9 . dac interrupt theirdac(dacinterruptrequest)flagwillbeset whilereload signalofdacoccurs.thenthedacinterruptwillb eexecuted ifiedac(dacinterruptenable)isset,andinterru ptdisable flagiscleared.hardwarewillpushpc, preg istertostack andsetinterruptmaskflag(i) .programcounterwillbeloaded withthedacvectorfromlocations$7ff6and$7ff7 . t0 interrupt theirt0(timer0interruptrequest)flagwillbese twhile timer0overflows.withiet0(timer0interruptenabl e)being set,thet0interruptwillexecute,andinterruptm askflagwillbe cleared.hardwarewillpushpc, pregisterto stackand setinterruptmaskflag(i) .programcounterwillbeloadedwith thet0vectorfromlocations$7ff4and$7ff5 . t1 interrupt theirt1(timer1interruptrequest)flagwillbese twhilet1 overflows.withiet1(timer1interruptenable)bein gset,the t1interruptwillexecute,andinterruptmaskflag willbecleared. hardwarewillpushpc, pregistertostackan dset interruptmaskflag(i) .programcounterwillbeloadedwiththe t1vectorfromlocations$7ff2and$7ff3 . pt interrupt theirpt(portainterruptrequest)flagwillbese twhileporta transitionsignaloccurs.withiept(ptinterrupte nable)being set,theptinterruptwillbeexecute,andinterrup tmaskflagwill becleared.hardwarewillpushpc, pregister tostackand setinterruptmaskflag(i) .programcounterwillbeloadedwith theptvectorfromlocations$7ff0and$7ff1 . bt interrupt theirbt(basetimerinterruptrequest)flagwillb esetwhen basetimeroverflows.thebtinterruptwillbeexec utedonce theiebt(btinterruptenable)issetandtheinter ruptmaskflag iscleared.hardwarewillpushpc, pregister tostackand setinterruptmaskflag(i) .programcounterwillbeloadedwith thebtvectorfromlocations$7feeand$7fef . lcd frame interrupt the irlcd (lcdframeinterruptrequest)flagwillbesetwhe n onenewdisplayframecyclestarts.thisinterrupt isveryuseful forsoftwaregrayscaledesign.thelcdframeinterr uptwillbe executedoncethe ielcd (lcdframeinterruptenable)isset andtheinterruptmaskflagiscleared.hardwarewi llpush pc and p registerstostackandsetinterruptdisableflag i . programcounter pc willbeloadedwiththelcdvectorfrom locations$7fecand$7fed. spi interrupt therearetwointerruptsforspitransmitterandre ceiver respectively. irstx (spitransmitterinterruptrequest)flagwill besetwhenspitransmitbufferisempty. irsrx (spireceiver interruptrequest)flagwillbesetwhenspicomple tesone receivingdataandthereceivebufferisready.the spi interruptswillbeexecutedoncetherelatedenable flag iesrx , iestx aresetandtheinterruptdisableflag i iscleared. hardwarewillpush pc , p registerstostackandset i flag . programcounterwillbeloadedwiththespivector from locations$7fe7,$7fe6,and$7fe9,$7fe8. uart interrupts thereare2interruptsforuart:receiverinterrupt (urx),and transmitterinterrupt(utx).urxhappenswhenrecei vedatais readyandthereceiverneedstobeserviced.utxha ppens whencurrenttransmissioniscompleted.errorsare indicatedby bitsofuartstatusregister( ustr ).othersequencesofuart interruptsarethesamewiththosedescriptionsabo ve.
ST2202A ver2.5 14 / 75 9/16/2008
ST2202A ver2.5 15 / 75 9/16/2008 9 9 . . g g p p i i o o thest2202consistsof48generalpurposei/o(gpio )which aredividedintosixi/oports:porta/b/c/d/eand portl. controlregistersofgpioareshownasfollowingan din table 91. portdataregisters: pa ~ pe, pl portdirectioncontrolregisters: pca ~ pce, pcl porttypeselectregisters: psc portfunctionselectregisters: pfc and pfd portmiscellaneouscontrolregister: pmcr table 9-1 summary of control registers of gpio address name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default $000 pa r/w pa[7] pa[6] pa[5] pa[4] pa[3] pa[2] pa[1] pa[0] 11111111 $001 pb r/w pb[7] pb[6] pb[5] pb[4] pb[3] pb[2] pb[1] pb[0] 11111111 $002 pc r/w pc[7] pc[6] pc[5] pc[4] pc[3] pc[2] pc[1] pc[0] 11111111 $003 pd r/w pd[7] pd[6] pd[5] pd[4] pd[3] pd[2] pd[1] pd[0] 11111111 $004 pe r/w pe[7] pe[6] pe[5] pe[4] pe[3] pe[2] pe[1] pe[0] 11111111 $04c pl r/w pl[7] pl[6] pl[5] pl[4] pl[3] pl[2] pl[1] pl[0] 11111111 $005 psc r/w psc[7] psc[6] psc[5] psc[4] psc[3] psc[2] psc[1] psc[0] 11111111 $008 pca r/w pca[7] pca[6] pca[5] pca[4] pca[3] pca[2] pca[1] pca[0] 00000000 $009 pcb r/w pcb[7] pcb[6] pcb[5] pcb[4] pcb[3] pcb[2] pcb[1] pcb[0] 00000000 $00a pcc r/w pcc[7] pcc[6] pcc[5] pcc[4] pcc[3] pcc[2] pcc[1] pcc[0] 00000000 $00b pcd r/w pcd[7] pcd[6] pcd[5] pcd[4] pcd[3] pcd[2] pcd[1] pcd[0] 00000000 $00c pce r/w pce[7] pce[6] pce[5] pce[4] pce[3] pce[2] pce[1] pce[0] 00000000 $04e pcl w pcl[7] pcl[6] pcl[5] pcl[4] pcl[3] pcl[2] pcl[1] pcl[0] 00000000 $00d pfc r/w rxd0 txd0 srdy ss mosi miso sck intx 00000000 $00e pfd r/w rxd1 txd1 cs6 cs5 cs4 cs3 cs2 cs1 00000000 $00f pmcr r/w pull pdbn integ csm1 csm0 bco tco1 tco0 10000000 eachsinglepincanbeprogrammedtobeinputorou tput.this iscontrolledbyportdirectioncontrolregisters pcx .settingbit of pcx makesrespectivepintooutput,andclearingthis bitfor input.therearetwooptions:pullup/downforinpu tsofportc butonlypullupforinputsoftheotherports.in caseofoutput, thereareopendrain/cmosoptionsforoutputsofpo rtcbut onlycmosfortheotherports.referto table92. table 9-2 i/o types of gpio ports i/o types i/o mode port-a/b/d/e/l port-c input pullup/pure pullup/pulldown/pure output cmos opendrain/cmos input mode incaseofinputfunction,portdataregisters px reflectthe valuesonassociatedpins.besidesreadinstruction fordataof signalsinput,writingtoregister px selectsi/otypesofpins, pulluporpulldown.settingbitsofallportdata register px to selectpulluptype.clearingbitsofonly pc toselectpulldown typeforpinsofportc.therearenopulldownres istorsfor porta/b/d/eandportl,therebynopulldownresis torswillbe enabledifclearingbitsof pa , pb , pd , pe and pl .pullup resistorsofporta/b/d/e/larealsocontrolledby pullbit(bit7 ofportmiscellaneousregister pmcr ),0istodisable,while 1istoenablethem.thepullup/pulldownresist orsofportc arefurthercontrolledbybitsofporttypeselect registers psc . theyworkinthesamewaywithpullbitof pmcr butonlyon singlepin,0istodisable,while1istoenab le.referto figure91. vcc portdata register (pdr) pullup pmos pullup rd_input datainput portcontrol register (pcr) figure 9-1 configuration of inputs output mode incaseofoutputfunction,writetoportdataregi sters px makespinstooutputdesiredvalue.thisvaluecan alsobe readbackbyreadinstruction.besidesportc,the outputpins arecmostype.portchavetwooptionsofoutputty pes: opendrainandcmos,andiscontrolledbyporttype select registers psc .clearingbitsofregisters psc isforthatdisable pmosofoutputstageandleftonlynmos,whilesett ingbitsis forcmos.referto figure92. figure 9-2 configuration of outputs
ST2202A ver2.5 16 / 75 9/16/2008 portaisdesignedforkeyboardscanwithdebounce and transitiontriggeredinterrupt,whileportc/d/ear emultiplexed withothersystemfunctions,andarecontrolledby pfc , pfd , and pmcr[2:0] .portlissharedwithlcdspecificsignalsof lcdc.turningofflcdcbysetting lpwr ( lctr[7] )reserves portlforgpio. selectingrespectivepinstobegpioorsignalsof system functionwillnotaffectoriginalsettingsofi/od irectionsand types.thisextendstheflexibilityoftheusageof function signals. note:allthepropertiesofpinsarestillprogramm able andmustbeascertainedbeforetheyare assignedtosystemfunctions,especiallythe directionofpins. table 9-3 port control registers address name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default $008~$00c / $07e pca~pce, pcl r/w pcx[7] pcx[6] pcx[5] pcx[4] pcx[3] pcx[2] pcx[1] pcx[0] 00000000 bit7~0: pcx[7:0] : portxdirectioncontrolbits 0 =inputmode 1=outputmode table 9-4 port data registers address name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default $000~$004 / $07c pa~pe, pl r/w px[7] px[6] px[5] px[4] px[3] px[2] px[1] px[0] 11111111 bit7~0: px[7:0] : portdata/pullresistorcontrolbits i/o modes r/w input mode output mode read inputdata write 0=disablepullupresistor selectpulldownresistor(portconly) 1 =selectpullupresistor outputdata table 9-5 port i/o type select registers address name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 def ault $005 psc r/w psc[7] psc[6] psc[5] psc[4] psc[3] psc[2] psc[1] psc[0] 11111111 bit7~0: psc[7:0] : porti/otypesselectionbits input mode output mode 0=disablepullup/downresisters 1 =enablepullup/downresisters 0=opendrain 1 =cmos table 9-6 port function select registers address name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default $00d pfc r/w rxd0 txd0 srdy ss mosi miso sck intx 00000000 $00e pfd r/w rxd1 txd1 cs6 cs5 cs4 cs3 cs2 cs1 00000000 bit7~0: pfc/d[7:0] : portfunctionselectbits 0 =gpio 1=indicatedfunctionsignalisconnected table 9-7 port miscellaneous control register (pmcr ) address name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default $00f pmcr r/w pull pdbn integ csm1 csm0 bco tco1 tco0 10000000 bit7: pull : enable/disableallpullupresistersofporta/b/d /e/l 1 =enablepullupresisters 0=disablepullupresisters
ST2202A ver2.5 17 / 75 9/16/2008 9.1 port-a transistion interrupt portaisdesignedforthereturnlineinputsofke yboardscan withtransitiontriggeredinterruptanddebounceo ption. differencebetweencurrentvalueandthedatakept previously ofportawillgenerateaninterruptrequest.thel aststateof portamustbelatchedbeforetransition,andthis canbedone byonereadinstructiontoporta.stepsandprogra mexample areshownbelow. operate port-a interrupt steps: 1. setinputmode. 2. readporta. 3. clearinterruptrequestflag(irpt). 4. setinterruptenableflag(iept). 5. clearcpuinterruptdisableflag(i). 6. readportabeforertiinstructioninisr example: . . stz ST2202A ver2.5 18 / 75 9/16/2008 9.1.1 port-a interrupt de-bounce thest2202hasahardwaredebounceblockforport a interrupt.itisenabledwith1anddisablewith 0of pdbn (pmcr[6]) .thedebouncefunctionisactivatedafterfirst portatransitionisdetected.itusesoscxasthe sampling clock.thedebouncetimeisoscxx512cycles(abo ut15.6 ms).datafilteredbydebouncepresentsastables tate,then theinterruptcanbeissued. table 9-8 port miscellaneous control register (pmcr ) address name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default $00f pmcr r/w pull pdbn integ csm1 csm0 to2 to1 to0 10000000 bit6: pdbn : enableportainterruptdebounce 1=debounceforportainterrupt 0 =nodebounceforportainterrupt 9.2 external interrupt pc0playsanotherfunctionofexternaledgesensiti veinterrupt source.fallingorrisingedgeiscontrolledbyint eg(pmcr[5]). stepsandprogramexampleareshownbelow. steps for intx interrupt operation: 1. setpc0toinputmode.(pcc[0]) 2. setpf0to1 3. selectedgelevel.(integ) 4. clearintxinterruptrequestflag.(irx) 5. setintxinterruptenablebits.(iex) 6. clearcpuinterruptmaskflag(i). example: . . rmb0 ST2202A ver2.5 19 / 75 9/16/2008 1 1 0 0 . . c c h h i i p p - - s s e e l l e e c c t t l l o o g g i i c c ( ( c c s s l l ) ) thest2202buildsinonechipselectsignal( cs0 )for embedded256kbytesmaskromandsixchipselectsi gnals multiplexedwithpd5~0ofportdwhichareusedto select externaldevicesontheaddressanddatabus.there aretwo optionsforthefirst256kbytesmemorywhicharec ontrolledby mmdpin.tiemmdtogroundtoselectnormalmodean d enableinternalromforthefirst256kbytesmemory .connect mmdtochipselectofanexternaldevicetoselect emulation modeanddisableinternalrom.afterresetcycles, mmd changestoanoutputandoutputschipselectsignal cs0 . referto figure101fortwoconnectionsofdifferentmodes. twobits csm[1:0] ofportmiscellaneousregister( pmcr ) selectfourmodesofcslwhichdefinethememorysi zeof eachexternalchipselect.if csm0 equals1,chipselect signal cs6 changestobeaddresssignala23tomakeone singledeviceof16mbytesat cs5 possible.theaddress rangeof csx ofhighernumberfollowstherangeofprevious oneoflowernumber.referto table102forconfigurationsof allchipselectsindifferentmodes. note:write1tobitofportdirectioncontrol register pcd ,thentobitofport functionselectregister pfd toactivatethe designatedchipselectsignal. a. normal mode b. emulation mode figure 10-1 connections of mmd/ cs0 table 10-2 memory configurations of chip-selects first256k external chipselect modes memoryrangeandsizeofchipselects totalsupport memorysize cs0 , mmd/ cs0 csm[1:0] cs1 cs2 cs3 cs4 cs5 cs6 /a23 00 $1000000~ $17fffff ( 8m bytes) $1800000~ $1ffffff ( 8m bytes) 01 $0400000~ $04fffff ( 1m bytes) $0500000~ $05fffff ( 1m bytes) $0600000~ $07fffff ( 2m bytes) $0800000~ $0ffffff ( 8m bytes) $1000000~ $1ffffff ( 16m bytes) a23 28m + 256k bytes 10 $2000000~ $27fffff ( 8m bytes) $2800000~ $2ffffff ( 8m bytes) $0000000~ $003ffff ( 256k byte) 11 $0400000~ $07fffff ( 4m bytes) $0800000~ $0ffffff ( 8m bytes) $1000000~ $17fffff ( 8m bytes) $1800000~ $1ffffff ( 8m bytes) $2000000~ $2ffffff ( 16m bytes) a23 44m + 256k bytes
ST2202A ver2.5 20 / 75 9/16/2008 table 10-3 port function select registers address name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 def ault $00e pfd r/w rx1 tx1 cs6 cs5 cs4 cs3 cs2 cs1 00000000 bit7~0: pfd[5:0] : portfunctionselectbits 0 =gpio 1=chipselectsignalisconnected table 10-4 port miscellaneous control register (pmc r) address name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default $00f pmcr r/w pull pdbn integ csm1 csm0 to2 to1 to0 10000000 bit1~0: csm[1:0] : externalchipselectmodeselectionbits see table102formoreinformation
ST2202A ver2.5 21 / 75 9/16/2008 1 1 1 1 . . c c l l o o c c k k g g e e n n e e r r a a t t o o r r thest2202hastwooscillatorsoscandoscxforbot h highandlowfrequencyneeded.whenoscillatormode selectionpin,xmd,isinputtedhighlevel,thehig h frequencyoscillatoroscadoptsonlyoneexternalr esistor togenerateahighfrequencyclockosckwhichisus edby almosteveryblockinchip.osccanalsochangeto bea resonator/crystaloscillatorbyinputlowlevelto xmd. thelowfrequencyoscillatoroscxneedsa32768hz crystalandonecapacitortogeneratoraprecisefr equency clk32forbasetimer,timer1andthereferencecloc kof baudrategenerator(bgr). otherclocksaresourcedfromeitherosckorclk32 and arelistedbelow: systemclock: sysck lcdcontrollerclock: lcdck psgandpwmdacclock: psgck bgroutputclock: bgrck spitransmissionclock: spick sysck thesystemclockcanbeswitchedbetweenosckand clk32byresettingorsetting xsel ( sys[7] ).after xsel is set(orreset),warmupcycleswillbeinitiatedat thesame time.theoriginalclockisstillconnecteduntilt heendof warmupcycles.clockbeingusedcanbereportedby reading xsel back. note:test xsel toconfirmsysckisswitched oversuccessfullybeforeturningdownthe originalclock. therearetwooptionsforwarmupcycles:16/256 cycles, whicharecontrolledby wskp ( sys[3] ).usually16cycles areenoughforoscandoscx. lcdck thelcdcontrollerhasonefourbitdividertogene rate lcdckdirectlyfromosckforpixelclockandother operations.thisdivideriscontrolledby lckr[3:0] andthe datamodeselectionbit lmod ( lckr[4] ).referto table 113forsettingsoflcdck. psgck psgckistheclockusedbypsgandpwmdac.itis sourcedfromoscktomakesureofonerightandhig h enoughbasefrequencyandtokeepitunchanged.bit sof psgc[6:4] controltheoptionsofpsgck.referto table 114fortheseoptions. bgrck thest2202equipsabaudrategenerator(bgr),whic his controlledbybgrcontrolregister bctr ,lockedfrequency selectionregister brs ,anddividercontrolregister bdiv . thebgrutilizesdigitalplltechniquetolockahi gh frequency high f aroundosck/2.thishighfrequencyis furtherscaleddownviaanintegerdividertoades ired frequencybgrck.thebgrusesclk32asreference clockforthemodulationofosck.therearetwo modulationmodeswhichcanbeselectedby bmod ( bctr[1] ).themodulationstrengthisalsocontrollableby settingorresetting bstr ( bctr[2] ). therelationbetweenlockedfrequencyand brs canbe foundinthefollowingequation. brs ? = 32 clk f high equation91 osckand high f arecloserelated.valueof high f limits thefrequencyrangeoftheosckapplied,whichisa lsothe lockingrangeofbgr,andisgivenbythefollowing equation,whereisthemodulationstrengthcoeffi cient. 1 f 2 osck 1 f high high ? ? + ? equation92 althoughthelockedfrequencyislimitedtobearou nd osck,lowerfrequencycanstillbeobtainedbyone 8bit integerdivider,whichisassignedby bdiv .thusbgrck canbeexpressedbyequation93. bdiv high f bgrck = equation93 spick thespiblockhasonethreebitdividertogenerate spick directlyfromosckfortransmissionandotheropera tions. thisdivideriscontrolledby sckr[6:4] .referto table 117forsettingsofspick.
ST2202A ver2.5 22 / 75 9/16/2008 osck sysck osc ostp (sys[6]) out oscx xstp (sys[5]) out sel wskp (sys[3]) clk32 mux2 in0 in1 xbak (sys[4]) heavy xsel (sys[7]) warm-up control 256 cycles 16 cycles normal en en ? ? ? lcdck lcdck divider lckr[4:0] in out osck,osck/2/4/30 osck, clk32 xsel (sys[7]) ina out inb psgck divider psgc[6:4] ? psgck ? osckx2,osck/2/4/8/16 clk32 bgr n integer divider bgrck in ref target bdiv[7:0] bsr[7:0] / bctr[2:0] in out out clk32xk ? spick spick divider sckr[6:4] in out osck/2/4/8/256 figure 11-1 clock generator diagram table 11-2 system control register (sys) address name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default r xsel ostp xstp wskp wait irren high 00000001 $030 sys w xsel ostp xstp wskp wait irren lvden 00000000 bit7: xsel : write:selectsourceofsystemclock(sysck)/rea d:reportofclocksourcebeingused 0 =osc 1=oscx bit6: ostp : oscstopcontrolbit 0 =enableosc 1=disableosc bit5: xstp : oscxstopcontrolbit 0 =enableoscx 1=disableoscx bit4: no used : pleasekeepthisbit0. bit3: wskp : systemwarmupcyclesselectionbit 0 =256warmupcycles 1=16warmupcycles
ST2202A ver2.5 23 / 75 9/16/2008 table 11-3 lcd clock control register (lckr) address name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default $048 lckr w lmod lck[3] lck[2] lck[1] lck[0] 00000 bit4: lmod :lcddatabusmodeselection 0 =1bitmode 1=4bitmode bit3~0: lckr[3:0] :lcdclockselection lcdck lckr[3:0] 1bitmode ( lmod = 0 ) 4bitmode ( lmod =1) 0000 osck 0001 osck/2 0010 /4 0011 osck /6 0100 /8 0101 /10 0110 /12 0111 osck/2 /14 1000 /16 1001 /18 1010 /20 1011 osck/4 /22 1100 /24 1101 /26 1110 /28 1111 osck/6 /30 table 11-4 psg control register (psgc) address name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default pck[2] pck[1] pck[0] prbs c1en c0en dace=0 0000000 $016 psgc r/w pck[2] pck[1] pck[0] dmd[1] dmd[0] inh dace=1 0000000 bit3~0: psgc[6:4] :psgclockselection pck[2:0] psgck 000 sysck/2 001 sysck/4 010 sysck/8 011 sysck/16 1xx sysck 111 clk32 table 11-5 bgr control register (bctr) address name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default $063 bctr r/w test bstr bmod bgren 0000 bit7: test :testbit,mustbe0 bit2: bstr :modulationstrengthselectionbit 0 =fullmodulationstrength (recommended) 1=halfmodulationstrength bit1: bmod :modulationmodeselectionbit 0 =coarsemodulationmode 1=finemodulationmode (recommended) bit0: bgren :bgrenable/disablebit 0 =disablebgr 1=enablebgr
ST2202A ver2.5 24 / 75 9/16/2008 table 11-6 bgr configuration registers (brs/bdiv) address name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default $066 brs r/w brs[7] brs[6] brs[5] brs[4] brs[3] brs[2] brs[1] brs[0] ???????? $067 bdiv r/w b div [7] b div [6] b div [5] b div [4] b div [3] b div [2] b div [1] b div [0] ???????? bgroutputfrequencysettings.seeequation91~9 3 table 11-7 spi clock control register address name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 def ault $053 sckr r/w sck[2] sck[1] sck[0] bc[3] bc[2] bc[1] bc[0] 0000000 bit6~4: sck[2:0] :spiclockselection sck[2:0] spick 000 sysck/2 001 sysck/4 010 sysck/8 011 sysck/16 100 sysck/32 101 sysck/64 110 sysck/128 111 sysck/256
ST2202A ver2.5 25 / 75 9/16/2008 1 1 2 2 . . t t i i m m e e r r / / e e v v e e n n t t c c o o u u n n t t e e r r 12.1 prescaler 12.1.1 function description thest2202hasthreetimers,basetimer,timer0an dtimer1, andtwoprescalerspresandprew.therearetwoclo ck sources,sysckandintx,forpresandoneclocksou rce, clk32,forprew.referto figure121 table 12-1 summary of timer registers address name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default $020 bten r/w bten[4] bten[3] bten[2] bten[1] bten[0] 00000 $021 btr r/w btr[4] btr[3] btr[2] btr[1] btr[0] 00000 r prs[7] prs[6] prs[5] prs[4] prs[3] prs[2] prs[1] prs[0] 00000000 $023 prs w sres sena sent 000 $024 t0m r/w t0m[5] t0m[4] t0m[2] t0m[1] t0m[0] 00 000 $025 t0c r/w t0c[7] t0c[6] t0c[5] t0c[4] t0c[3] t0c[2] t0c[1] t0c[0] 00000000 $026 t1m r/w t1m[4] t1m[3] t1m[2] t1m[1] t1m[0] 00000 $027 t1c r/w t1c[7] t1c[6] t1c[5] t1c[4] t1c[3] t1c[2] t1c[1] t1c[0] 00000000 r xsel ostp xstp wskp wait irren high 00000001 $030 sys w xsel ostp xstp wskp wait irren lvden 00000000 $03c ireq r/w irbt irpt irt1 irt0 irdac irx 000000 $03e iena r/w iebt iept iet1 iet0 iedac iex 000000 figure 12-1 structure of two prescalers
ST2202A ver2.5 26 / 75 9/16/2008 12.1.2 pres theprescalerpresisan8bitscounterasshownin figure 121. which provides four clock sources for base ti mer and timer1,anditiscontrolledbyregisterprs.thei nstructionread towardprswillbringoutthecontentofpresandt he instruction write toward prs will reset, enable or select clock sourcesforpres. whenusersetexternalinterruptastheinputofpr esforevent counter, combining pres and timer1 will get a 16bit event counter . table 12-2 prescaler control register (prs) address name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default r prs[7] prs[6] prs[5] prs[4] prs[3] prs[2] prs[1] prs[0] 00000000 $023 prs w sres sena sent 000 read bit7~0: prs[7~0] : valueofprescounter write bit7: sres : prescalerresetbit write1toresettheprescaler(prs[7~0]) bit6: sena : prescalerenablebit 0=disableprescalercounting 1=enableprescalercounting bit5: sent : clocksource(tclk)selectionforprescallerpres 0=clocksourcefromsystemclocksysck 1=clocksourcefromexternaleventsintx 12.1.3 prew the prescaler prew is an 8bits counter as shown in figure 116. prew provides four clocks source for base tim er and timer1.itstopscountingonlyifoscxstopsorhar dwarereset occurs.
ST2202A ver2.5 27 / 75 9/16/2008 12.2 base timer thebasetimersupportsoneinterrupt,whichoccurs atfive differentrates.applicationsbaseonthebasetime rinterrupt canchoseanappropriateinterruptratefromfivet imebasesfor theirspecificneeds.theserealtimeapplications mayinclude digitizersampling,keyboarddebouncing,orcommuni cation polling.blockdiagramofbasetimerisshownin figure122. 2048hz counter 256hz counter 64hz counter 8hz counter 2hz counter clk32 control register basetimer interrupt figure 12-2 base timer block diagram 12.2.1 base timer operations thebasetimerconsistsoffivesubcounterstopro ducefive predefinedrates.theconnectionsbetweenoverflow signalsof thesesubcountersandthebasetimerinterruptare controlled byrespectivebitfieldsofbasetimerenableregis ter( bten ). theenabledoverflowsignalsareoredtogeneratet hebase timerinterruptrequest.relatedbitsofbasetimer statusregister ( btsr )willshowwhichratesofinterruptsshouldbeser viced. write1to btclr (bit7of btsr) mayclearthisregister. note:makesure btsr isclearedaftertheinterrupt wasserviced,sothattherequestcanbesetnext time. 12.2.2 base timer control/status registers summaryofbasetimercontrol/statusregistersiss hownin table123. table 12-3 summary of base timer control registers address name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default $020 bten r/w bten[4] bten[3] bten[2] bten[1] bten[0] 00000 r btsr[4] btsr[3] btsr[2] btsr[1] btsr[0] 00000 $021 btsr w btclr 0 $03c ireq r/w irlcd irbt irpt irt1 irt0 irdac irx 0000000 $03e iena r/w ielcd iebt iept iet1 iet0 iedac iex 0000000 base timer control register table 12-4 base timer control register (bten) address name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default $020 bten r/w bten[4] bten[3] bten[2] bten[1] bten[0] 00000 bit0: bten0 : 2hzinterruptcontrolbit 0 =disable2hzinterrupt 1=enable2hzinterrupt bit1: bten1 : 8hzinterruptcontrolbit 0 =disable8hzinterrupt 1=enable8hzinterrupt bit2: bten2 : 64hzinterruptcontrolbit 0 =disable64hzinterrupt 1=enable64hzinterrupt bit3: bten3 : 256hzinterruptcontrolbit 0 =disable256hzinterrupt 1=enable256hzinterrupt bit4: bten4 : 2048hzinterruptcontrolbit 0 =disable2048hzinterrupt 1=enable2048hzinterrupt
ST2202A ver2.5 28 / 75 9/16/2008 base timer status register table 12-5 base timer status register (btsr) address name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default r btsr[4] btsr[3] btsr[2] btsr[1] btsr[0] 000000 $021 btsr w btclr 0 bit0: btsr0 : 2hzinterruptstatusbit 0 =no2hzinterruptoccurred 1=2hzinterruptoccurred bit1: btsr1 : 8hzinterruptstatusbit 0 =no8hzinterruptoccurred 1=8hzinterruptoccurred bit2: btsr2 : 64hzinterruptstatusbit 0 =no64hzinterruptoccurred 1=64hzinterruptoccurred bit3: btsr3 : 256hzinterruptstatusbit 0 =no256hzinterruptoccurred 1=256hzinterruptoccurred bit4: btsr4 : 2048hzinterruptstatusbit 0 =no2048hzinterruptoccurred 1=2048hzinterruptoccurred bit7: btclr : write1toclearallstatusbit
ST2202A ver2.5 29 / 75 9/16/2008 12.3 timer 0 12.3.1 function description thetimer0isan8bitupcounter.itcanbeuseda satimeror aneventcounter.t0c($25)isarealtimeread/writ ecounter. whenanoverflowfrom$ffto$00,atimerinterrupt request irt0will begenerated.timer0willstopcountingwhensystem clock stops.pleasereferto figure123. in0in1 in2 in3 in4 in5 in6 in7 sel out pres mux81 t0m[2~0] tclk/65536 tclk/32768 tclk/8192 tclk/2048 tclk/256 tclk/32 tclk/8 tclk/2 t0m[4]t0m[5] reload enable clock 8bitupcounter out irt0 auto d q ck d flip-flop sysck figure 12-3 timer0 structure 12.3.2 timer0 clock source control severalclocksourcescanbechosenfromfortimer0 .itsvery importantthattimer0cankeepcountingaslongas sysck staysactive .referto table126. table 12-6 clock sources of timer0 t 0 m [2 ] t 0m [1 ] t 0 m [0 ] t 0 t im e rc lo c k s o u rc e 0 0 0 t c l k /6 5 5 3 6 0 0 1 t c l k /3 2 7 6 8 0 1 0 t c l k /8 1 9 2 0 1 1 t c l k /2 0 4 8 1 0 0 t c l k /2 5 6 1 0 1 t c l k /3 2 1 1 0 t c l k /8 1 1 1 t c l k /2 t0m[4]:controlautomaticreloadoperation 0:noautoreload 1:autoreload t0m[5]:controltimer0enable/disable 0:disablecounting 1:enablecounting sena :prescalerenablebit 0:tclkstop 1:tclkcounting table 12-7 timer0 register (t0c) address name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default $025 t0c r/w t0c[7] t0c[6] t0c[5] t0c[4] t0c[3] t0c[2] t0c[1] t0c[0] 00000000 bit70: t0c[7-0] : timer0upcounterregister
ST2202A ver2.5 30 / 75 9/16/2008 12.4 timer 1 thetimer1isan8bitupcounter.itusedastimer /counterasprogramspecified.thedifferencebetwe enbasetimeristhattimer1 willhaltduringcpusby,butbasetimerwillnot. itisshownin figure124. in4in5 in6 in7 sel pres t1m[2~0] mux41 prew in0in1 in2 in3 sel t1m[1~0] mux 8bitupcounter clock irt1 mux81 oscx/256oscx/128 oscx/64 bgrck tclk/256 tclk/32 tclk/8 tclk/2 out out in0in1 out sel d ck q dflipflop sysck mux t1m[3] autoreload t1m[4] in0in1 in2 in3 tclk/65536tclk/32768 tclk/8192 tclk/2048 figure 12-4 timer1 structure table 12-8 timer1 register (t1c) address name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default $027 t1c r/w t1c[7] t1c[6] t1c[5] t1c[4] t1c[3] t1c[2] t1c[1] t1c[0] 00000000 bit70: t1c[7-0] : timer1upcounterregister table 12-9 clock sources of timer1 t1m[3] t1m[2] t1m[1] t1m[0] t1timerclocksource 0 0 0 0 tclk/65536 0 0 0 1 tclk/32768 0 0 1 0 tclk/8192 0 0 1 1 tclk/2048 0 1 0 0 tclk/256 0 1 0 1 tclk/32 0 1 1 0 tclk/8 0 1 1 1 tclk/2 1 0 0 0 oscx/256 1 0 0 1 oscx/128 1 0 1 0 oscx/64 1 0 1 1 bgrck t1m[4]:controlautomaticreloadoperation 0:noautoreload 1:autoreload sena:prescalerenablebit 0:tclkstop 1:tclkcounting
ST2202A ver2.5 31 / 75 9/16/2008 1 1 3 3 . . c c l l o o c c k k i i n n g g o o u u t t p p u u t t s s threeclockingoutputspe0,pe1andpe2aresupport edby thest2202.thesesignalsareveryusefulforoutpu tsofhigh frequency,suchaspwmbasesignalorcarrierofre mote control.timer0,timer1overflowsignalsareclock sourcesfor pe0andpe1,whilebgrckareforpe2. clocking outputs: pe0 and pe1 overflowstatesoftimerswillbeconnectedtotogg ledataof pe[0:1] whensettingfunctionselectionbits tco0/tco1 ( pmcr[0:1] ).meanwhilepe0/pe1outputclockeddataofhalf thefrequencyoftimers.afterresetting tco0/tco1 ,thetoggle operationceases.thenpe0/pe1returntotheorigin allogic levelof pe[0:1] . clocking output: pe2 bgrckwilloutputthroughpe2whensettingfunction selection bit bco ( pmcr[2] ).if bco iscleared,pe2returnstothe originallogiclevelof pe[2] . summaryofclockingoutputsregistersisshownin table131. theclockingoutputsenablebitscanbefoundin table132. table 13-1 summary of clocking outputs registers address name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 def ault $004 pe r/w pe[7] pe[6] pe[5] pe[4] pe[3] pe[2] pe[1] pe[0] 11111111 $00c pce r/w pce[7] pce[6] pce[5] pce[4] pce[3] pce[2] pce[1] pce[0] 00000000 $00f pmcr r/w pull pdbn integ csm1 csm0 bco tco1 tco0 1000000 table 13-2 port miscellaneous control register (pmc r) address name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default $00f pmcr r/w pull pdbn integ csm1 csm0 bco tco1 tco0 10000000 bit0: tco0 : clockingoutputpe0controlbit(sourcedfromtime r0) 0 =disableclockingoutputofpe0 1=enableclockingoutputofpe0 bit1: tco1 : clockingoutputpe1controlbit(sourcedfromtime r1) 0 =disableclockingoutputofpe1 1=enableclockingoutputofpe1 bit2: bco : clocksignaloutputpe2controlbit(sourcedfrom bgrck) 0 =disableclocksignaloutputofpe2 1=enableclocksignaloutputofpe2
ST2202A ver2.5 32 / 75 9/16/2008 1 1 4 4 . . p p s s g g 14.1 function description thebuiltindualchannelprogrammablesoundgenera tor (psg)iscontrolledbyregisterfiledirectly.its flexibilitymakesit usefulinapplicationssuchasmusicsynthesis,sou ndeffects generation,audiblealarmsandtonesignaling.ino rderto generatesoundeffectswhileallowingtheprocessor toperform othertasks,thepsgcancontinuetoproducesound afterthe initialcommandshavebeengivenbythecpu.thest ructureof psgwasshownin figure142andthepsgclocksourceis shownin figure141.thest2202hasthreepsgplaying type.oneforchannel0(c0)&channel1(c1)squarety petone soundplaying.secondforch0squaretonesoundand ch1 noisesound.thethirdsoundplayingtypeisdacpc mplaying. rc oscx psgc[6~4] in0 in1 output select psgselector psgck psgc sysck/2 psgck sysck/4 sysck/8 sysck/16 sysck oscx b6 b5 b4 0 0 0 x x 0 1 1 1 1 1 1 1 0 1 0 0 0 figure 14-1 psg clock source control enable output enableload output mux2 in0in1 output sel mux2 in0in1 output sel mux2 in0in1 output sel mixer ch1 output vol_ch1 dace c1ten c1tone c1out dacepsgc[2] c1nen c1noise psgc[3] psg0 c1out vol[1~0] psg1 bd bdb dace toportb fromdacgenerator channel1tone channel1noise preloaddatabeforefirstcount figure 14-2 psg block diagram
ST2202A ver2.5 33 / 75 9/16/2008 table 14-1 summary of psg registers address name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default $010 psg0l w psg0[7] psg0[6] psg0[5] psg0[4] psg0[3] psg0[2] psg0[1] psg0[0] 00000000 $011 psg0h w psg0[11] psg0[10] psg0[9] psg0[8] 0000 $012 psg1l w psg1[7] psg1[6] psg1[5] psg1[4] psg1[3] psg1[2] psg1[1] psg1[0] 00000000 $013 psg1h w psg1[11] psg1[10] psg1[9] psg1[8] 0000 w pck[2] pck[1] pck[0] prbs c1en c0en dace=0 0000000 $016 psgc w pck[2] pck[1] pck[0] dmd[1] dmd[0] inh dace=1 0000000 $017 vol w vol1[3] vol1[2] vol1[1] vol1[0] vol0[3] vol0[2] vol0[1] vol0[0] 00000000 table 14-2 psg volume control register (vol) address name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default $017 vol w vol1[3] vol1[2] vol1[1] vol1[0] vol0[3] vol0[2] vol0[1] vol0[0] 00000000 bit3~0: vol0[3~0] : psgchannel0volumecontrolbit 0000=nosoundoutput 0001=1/16volume (psgckmust>=320kh z) : 0100=4/16volume : 1000=8/16volume : 1111=maximumvolume (psgckmust>=20khz) bit7~4: vol1[3~0] : psgchannel1volumecontrolbit 0000=nosoundoutput 0001=1/16volume (psgckmust>=320k hz) : 0100=4/16volume : 1000=8/16volume : 1111=maximumvolume (psgckmust>=20khz) note: if single channel is enable, then psg volume control can be double. (16 + 16 = 32 level volume control)
ST2202A ver2.5 34 / 75 9/16/2008 14.2 tone generator 14.2.1 general description thetonefrequencyisdecidedbypsgckand12bitp rogrammabledivider(psg[11~0]).pleasereferto figure143 and. figure144. 12bitautoreloadupcounter toneout output psg0[11~8] psg0[7~0] load c0enpsgck c0[11~8] c0[7~0] latch enable frequencyofchannel0tone=psgck/(1000hpsg0[11~0])/2 clock channel0 figure 14-3 tone generator channel 0 12bitautoreloadupcounter toneout output psg1[11~8] psg1[7~0] load c1enpsgck c1[11~8] c1[7~0] latch enable frequencyofchannel1tone=psgck/(1000hpsg1[11~0])/2 clock channel1 figure 14-4 tone generator channel 1 14.2.2 psg tone programming settingpsgcontrolbit dace ( psgc[0] )willmakepsg blockfunctionsasasoundgeneratorof2channels. setting c1en willenabletonegeneratorwhenpsgisintone function.noiseortonefunctionisselectedby prbs .
ST2202A ver2.5 35 / 75 9/16/2008 table 14-3 psg control register (psgc) address name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default w pck[2] pck[1] pck[0] prbs c1en c0en dace=0 0000000 $016 psgc w pck[2] pck[1] pck[0] dmd[1] dmd[0] inh dace=1 0000000 bit0: dace : tone(noise)ordacgeneratorselectionbit 1=psgisusedasthedacgenerator 0=psgisusedasthetone(noise)generator bit1: c0en : psgchannel0(tone)enablebit 1=psg0(tone)enable 0=psg0(tone)disable bit2: c1en : psgchannel1(toneornoise)enablebit 1=psg1(toneornoise)enable 0=psg1(toneornoise)disable bit3: prbs : toneornoisegeneratorselectionbit 1=noisegenerator 0=tonegenerator 14.3 noise generator control 14.3.1 general description noisegeneratorisshownin figure145,whichbasefrequencyiscontrolledby psg1[5~0]. psg1[5~0] psgck noiseprescaler c1n[5~0] clock output nck clock output 16stagewhitenoisegenerator noiseout nckfrequency=psgck/(40hpsg1[5~0]) figure 14-5 noise generator 14.3.2 noise generator programming dacedefinesnoiseordacfunction.writinga1t oc1en willenablenoisegeneratorwhenpsgisinn oisemode.
ST2202A ver2.5 36 / 75 9/16/2008 1 1 5 5 . . p p w w m m d d a a c c abuiltinpwmdacisforanalogsamplingdataorv oice signals.thestructureofdacisshownin table151. thereisaninterruptsignalfromdactocpuwhenev er dacdataupdateisneededandthesamesignalwill decide thesamplingrateofvoice.indacmode,thefreque ncyof rcoscillatorcantless2mhz. table 15-1 summary of dac registers address name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default $012 psg1l w psg1[7] psg1[6] psg1[5] psg1[4] psg1[3] psg1[2] psg1[1] psg1[0] 00000000 $013 psg1h w psg1[11] psg1[10] psg1[9] psg1[8] 0000 $014 dac w dac[7] dac[6] dac[5] dac[4] dac[3] dac[2] dac[1] dac[0] 00000000 $016 psgc w pck[2] pck[1] pck[0] dmd[1] dmd[0] inh dace=1 0000000 table 15-2 dac data register (dac) address name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 def ault $014 dac w dac[7] dac[6] dac[5] dac[4] dac[3] dac[2] dac[1] dac[0] 00000000 bit7~0: dac[7~0] : dacoutputdata note:forsinglepinsingleendedmode,theeffecti veoutputresolutionis7bit. table 15-3 dac control register (psgc) address name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 def ault $016 psgc w pck[2] pck[1] pck[0] dmd[1] dmd[0] inh dace=1 0000000 bit0: dace : psgplayastone(noise)ordacgeneratorselectio nbit 1=psgisusedasdacgenerator 0=psgisusedastone(noise)generator bit1: inh : dacoutputinhibitcontrolbit 1=dacoutputinhibit 0=dacoutputenable bit3~2: dmd[1~0] : dacoutputmodeselection 00=singlepinmode :7bitresolution 01=twopintwoendedmode :8bitresolution 10=reserved 11=twopinpushpullmode :8bitresolution
ST2202A ver2.5 37 / 75 9/16/2008 15.1 sample rate control psg1landpsg1hcontrolthesamplerate.psg1[11~6] controlspwmrepeattimes(usuallyset=111100forf our timesofdacreload)andpsg1[5~0]usuallyset1 .the inputclocksourceiscontrolledbypck[2~0].theb lock diagramisshownasthefollowing: samplerategenerator ck_inenable output psg1[11~0] pwmgenerator dac[7~0]enable fs po pob reload_dac inh dac[7~0] dmd[0]dmd[1] bd psg1[11~0] psgck fs bdb dace reload_dac dmd[0]dmd[1] figure 15-1 dac diagram rc oscx psgc[6~4] in0 in1 output select psgselector psgck psgc sysck/2 psgck sysck/4 sysck/8 sysck/16 sysck oscx b6 b5 b4 0 0 0 x x 0 1 1 1 1 1 1 1 0 1 0 0 0 figure 15-2 dac clock source control table 15-4 dac sample rate description (rc osc = 2mhz) dacinterruptfrequency pwmfrequency psgcb6,b5, b4 psg1h,psg1l 8k 32k 100 00001111,00111111 16k 32k 100 00001111,10111111
ST2202A ver2.5 38 / 75 9/16/2008 15.2 pwm dac mode options thepwmdacgeneratorhasthreemodes,singlepin mode,twopintwoendedmodeandtwopinpushpull mode.theyaredependedontheapplicationused.th e dacmodeiscontrolledbydmd[1~0]. (table133) 15.2.1 single-pin mode (7-bit accuracy) singlepinmodeisdesignedforusewithasinglet ransistor amplifier.ithas7bitsofresolution.thedutycy cleofthe psg1isproportionaltotheoutputvalue.iftheou tputvalue is0,thedutycycleis50%.astheoutputvaluein creases from0to63,thedutycyclegoesfrombeinghigh5 0%of thetimeupto100%high.asthevaluegoesfrom0 to64, thedutycycledecreasesfrom50%highto0%.psg0 is inverseofpsg1swaveform.figure133showsthep sg1 waveforms. dac = 0 64 64 dac = 32 dac = -32 dac = x 96 32 32 96 64+x 64-x high low psg1 figure 15-3 single-pin mode wave form
ST2202A ver2.5 39 / 75 9/16/2008 15.2.2 two-pin two ended mode (8-bit accuracy) twopintwoendedmodeisdesignedforusewithas ingle transistoramplifier.itrequirestwopinthat psg0 and psg1 . whenthedacvalueispositive, psg1 goeshighwitha dutycycleproportionaltotheoutputvalue,while psg0 stayshigh.whenthedacvalueisnegative, psg0 goes lowwithadutycycleproportionaltotheoutputva lue,while psg1 stayslow.thismodeoffersaresolutionof8bits . figure135showsexamplesofdacoutputwaveforms with differentoutputvalues.eachpulseofthedacisd ivided into128segmentspersampleperiod.forapositive output valuex=0to127, psg1 goeshighforxsegmentswhile psg0 stayshigh.foranegativeoutputvaluex=0to12 7, psg0 goeslowfor|x|segmentswhile psg1 stayslow. figure 15-4 two-pin two ended mode wave-form high low psg0 dac = x where x=0 to 127 dac = 96 high low psg1 x 128-x dac = 32 dac = 127 127 1 96 32 32 96 high low psg0 dac = x where x=0 to -128 dac = 0 high low psg1 |x| 128+x dac = -48 dac = -128 48 80
ST2202A ver2.5 40 / 75 9/16/2008 15.2.3 two-pin push pull mode (8-bit accuracy) twopinpushpullmodeisdesignedforbuzzer.itr equires twopinthat psg0 and psg1 .whenthedacvalueis0, bothpinsarelow.whenthedacvalueispositive, psg1 goeshigh withadutycycleproportionaltotheou tput value,while psg0 stayslow.whenthedacvalueis negative, psg0 goeshigh withadutycycleproportional totheoutputvalue,while psg1 stayslow.thismodeoffers aresolutionof8bits. figure137showsexamplesofdacoutputwaveforms with differentoutputvalues.eachpulseofthedacisd ivided into128segmentspersampleperiod.forapositive output valuex=0to127, psg1 goeshighforxsegmentswhile psg0 stayslow.foranegativeoutputvaluex=0to127 , psg0 goeshighfor|x|segmentswhile psg1 stayslow. figure 15-5 two-pin push pull mode wave form high low psg0 dac = x where x=0 to 127 dac = 96 high low psg1 x 128-x dac = 32 dac = 127 127 1 96 32 32 96 high low psg0 dac = x where x=0 to -128 dac = 0 high low psg1 |x| 128+x dac = -48 dac = -128 48 80
ST2202A ver2.5 41 / 75 9/16/2008 1 1 6 6 . . l l c c d d c c o o n n t t r r o o l l l l e e r r ( ( l l c c d d c c ) ) thelcdcontroller(lcdc)providesdisplaydataand specificsignalsforexternallcddriverstodrive thestn lcdpanels.thelcdcfetchesdisplaydatadirectly from internalsystemmemorythroughoneuniquememorybu s. thespecialdesignedinternalbussharesalmostnon eof thecpuresourcestomakebothfastdisplaydatapr ocess andhighspeedcpuoperationpossible.thest2202 buildsin4kbytessram,sothemaximumpanelsize can be240x120.thelcdcalsosupportssoftwaregraysca leto richthedisplayinformationandthediversityofc ontentsas well. lcdckisforlcdctogeneratetimingsandthepixel clock. referto table113forfrequencysettingsoflcdck. thest2202supports1and4bitdatabusforthe compatibilityofmostpopularlcddrivers.thelcd output signalsaresharedwithportl.,andarecontrolled bylcd powercontrolbit lpwr ( lctl[7] )anddatabusselection bit lmod ( lck[4] ).incaseof1bitmode,pl3~1ofportl canstillbeusedforgeneralpurpose. note:thelcdsignalswillbedisconnectedand portlwilloutputvaluesassignedby pl afterclearing lpwr . variousfunctionsarealsosupportedtorichthedi splay information,includingvirtualscreen,panning,scr olling, contrastcontrolandanalternatingsignalgenerato r.control registersusedbylcdcarelistedbelow. table 16-1 summary of lcd control registers address name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 def ault $040 lssal w ssa[7] ssa[6] ssa[5] ssa[4] ssa[3] ssa[2] ssa[1] ssa[0] 00000000 $041 lssah w ssa[15] ssa[14] ssa[13] ssa[12] ssa[11] ssa[10] ssa[9] ssa[8] 00000000 $042 lvpw w vp[7] vp[6] vp[5] vp[4] vp[3] vp[2] vp[1] vp[0] 00000000 $043 lxmax r/w xm[7] xm[6] xm[5] xm[4] xm[3] xm[2] xm[1] xm[0] 00000000 $044 lymax r/w ym[7] ym[6] ym[5] ym[4] ym[3] ym[2] ym[1] ym[0] 00000000 $045 lpan r/w pan[2] pan[1] pan[0] 000 $047 lctr r/w lpwr blnk rev 100 $048 lck w lmod lck[3] lck[2] lck[1] lck[0] 00000 $049 lfra w fra[5] fra[4] fra[3] fra[2] fra[1] fra[0] 000000 $04a lac r/w ac[4] ac[3] ac[2] ac[1] ac[0] 00000 $04b lpwm r/w lpwm[5] lpwm[4] lpwm[3] lpwm[2] lpwm[1] lpwm[0] 000000 $04c pl r/w pl[7] pl[6] pl[5] pl[4] pl[3] pl[2] pl[1] pl[0] 111 11111 $04e pcl w pcl[7] pcl[6] pcl[5] pcl[4] pcl[3] pcl[2] pcl[1] pcl[0] 00000000 16.1 lcd specific signals thefollowingsignalsaregeneratedbylcdctoconn ect theST2202Andanlcdpanel.twoofthemarededica ted outputpins,whiletheresteightpinsaremultiple xedwith portl. flm (pl7) thelcdframemarkersignalindicatesthestartof anew displayframe.flmbecomesactiveafterthelastli nepulse oftheframeandremainsactiveuntilthenextline pulse,at whichpointitdeassertsandremainsinactiveunti lthenext frame. load (pl6) thelcdlinepulsesignalisusedtolatchalineo fshifted datatothesegmentdriversoutputsandisalsous edto shiftthelineenablesignalofcommondriver.all thedriver outputsthencontroltheliquidcrystaltoformthe desired frameonpanel. ac (pl5) thelcdalternatesignaltogglesthepolarityofli quid crystalonthepanel.thissignalcanbeprogrammed to toggleforaperiodof1to31linesoroneframe. see section 16.4.7forregistersettings. cp (pl4) thelcdshiftclockpulsesignalistheclockoutpu ttowhich theoutputdatatothelcdpanelissynchronized.d atafor segmentdriversisshiftedintotheinternallineb ufferat eachfallingedgeofcp. ld3~0 (pl3~0) thelcddatabuslinestransferpixeldatatothel cdpanel sothatitcanbedisplayed.twokindsofdatabuss es,1 and4bit,aresupportedandarecontrolledby lmod ( lck[4] ).incaseof1bitmode, lmod shouldbecleared andthelcdcusesonlyld0totransferdata.ld3~1 can stillbeprogrammedtobenormalinputsoroutputs. the outputpixeldatacanbeinvertedthroughprogrammi ng. setting rev ( lctr )willreversetheoutputdataondata bus. poff (power control) thelcdpowercontrolsignalisusedtoturnon/off the
ST2202A ver2.5 42 / 75 9/16/2008 externaldcdcconverter,whichgeneratesahighvo ltage fordrivingliquidcrystal. poff outputs1whenclearing lpwr ( lctr ),andoutputs0bysettingthisbit,whichis alsothedefaultvalue. blank (contrast control) thelcdblanksignalisusedtocontrolthecontras tof displaybysettingcontrastlevelin lpwm[5:0] with00000 (default)representsamaximumleveland11111is for minimum.the blank signalachievesthisfunctionby outputtingapwmsignalaccordingtothesettingso f contrast.refertosection 16.4.10formoreinformation. besidescontrastcontrol, blank signalplaysanotherrole ofturningdisplayoff.thisiscontrolledbyregis terbit blnk ( lctr ).setting blnk bitwillmake blank signalto output0toblankthedisplayregardlessofcontr astcontrol. setting blnk bitwillenablethepwmcontrastcontroland ofcoursethe blank signal.if lpwmtr[5:0] areallzeros, blank signalwillstayathighlevelwithnopwm modulation. 16.2 mapping the display data thescreenwidthandheightofthelcdpanelare programmablethroughsoftware. figure161illustrates therelationshipbetweentheportionofalargegra phicsfile displayedonthescreenandtheactualpage.althou ghthe maximumscreensizecanbeupto1024x512,theactu al supportedresolutionislimitedbythedisplaybuff ersize, whichisalsotheinternalramsize,4kbytes.each bitin thedisplaymemorycorrespondstoapixelinthelc dpanel. figure161alsoshowsthemappingofthedisplayd ata tothelcd. figure 16-1 lcd screen format 16.3 lcd interface timing thelcdcontrollercontinuouslypumpsthepixeldat ainto thelcdpanelviathelcddatabus.thebusistime dby thecp,load,andflmsignals.twokindsofdatawi dth,1 and4bit,aresupportedformostmonochromelcdpa nels. referto figure162forboth1and4bitinterfacetiming.
ST2202A ver2.5 43 / 75 9/16/2008 figure 16-2 lcd interface timing for 1-/4-bit data 16.4 control registers 16.4.1 lcd screen starting address register thelcdscreenstartingaddressregister( lssa )isusedtoinformthestartingaddressofcurrent displaybuffer.different lcdframescanbeswitchedquicklybysimplymodify ingcontentof lssa .thelcdcontrollerwillstartfetchingpixeldata fromsystemmemoryatthisaddress. table 16-2 lcd screen starting address register address name r/w bit 7/15 bit 6/14 bit 5/13 bit 4/12 bit 3/11 bit 2/10 bit 1/9 bit 0/8 default $040 lssal w ssa[7] ssa[6] ssa[5] ssa[4] ssa[3] ssa[2] ssa[1] ssa[0] 00000000 $041 lssah w ssa[15] ssa[14] ssa[13] ssa[12] ssa[11] ssa[10] ssa[9] ssa[8] 00000000 bit15~0: lssa[15:0] :16bitstartingaddressofdisplaybuffer 16.4.2 lcd virtual page width register thelcdvirtualpagewidthregister( lvpw )containsthewidthofavirtualscreenthatmayb ewiderthanrealsetting.this fieldisusedforcalculatingthestartingpointof nextline. table 16-3 lcd virtual page width register address name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 def ault $042 lvpw w vp[7] vp[6] vp[5] vp[4] vp[3] vp[2] vp[1] vp[0] 0 0000000 bit7~0: vp[7:0] :widthofvirtualpagewidth virtualpagewith= lvpw *16 16.4.3 lcd screen width register thelcdscreenwidthregister( lxmax )isusedtospecifythewidthofthelcdpanelin pixels.everybitofdisplaydata mapstoonepixeloflcdpanel. lxmax representsnumberofdatainbyteofeachline.
ST2202A ver2.5 44 / 75 9/16/2008 table 16-4 lcd screen width register address name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 def ault $043 lxmax r/w xm[7] xm[6] xm[5] xm[4] xm[3] xm[2] xm[1] xm[0] 000 00000 bit7~0: xm[7:0] :lcdscreenwidth lcdscreenwidth= lxmax *8 16.4.4 lcd screen height register thelcdscreenheightregister( lymax )isusedtospecifytheweightofthelcdpanelin pixels. table 16-5 lcd screen height register address name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 def ault $044 lymax r/w ym[7] ym[6] ym[5] ym[4] ym[3] ym[2] ym[1] ym[0] 000 00000 bit7~0: ym[7:0] :lcdscreenheight lcdscreenheight= lymax *2 16.4.5 lcd panning offset register thelcdpanningoffsetregister( lpan )isusedtocontrolhowmanypixelsthepictureis shiftedtotheleft.valuesfrom0to7 canbefilledintothisregistertodenotetheoffs et,while0meansnopanningcontrol. table 16-6 lcd panning offset register address name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 def ault $045 lpan r/w pan[2] pan[1] pan[0] 000 bit2~0: pan[2:0] :lcdpanningoffsetfromzeroto7pixelsmax. 16.4.6 lcd control register thelcdcontrolregister( lctr )controlstheenablingswitchoflcdc,displaypan elon/offorreverseandthepwmcontrast controlblock. table 16-7 lcd control register address name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 def ault $047 lctr r/w lpwr blnk rev 100 bit7: lpwr :lcdcenable/disablebit 0 =enablelcdc( poff signaloutputshighlevel) 1=disablelcdc( poff signaloutputslowlevel) bit6: blnk :lcddisplayon/offbit 0 =lcddisplayon( blank signaloutputscontrastcontrolsignal) 1=lcddisplayoff( blank signaloutputslowlevel) bit5: rev :lcddisplayreverse 0 =normaldisplay 1=reversedisplay
ST2202A ver2.5 45 / 75 9/16/2008 16.4.7 lcd frame rate adjust register thelcdframerateadjustregister( lfra )specifiesthe extendedtimeofeachscanline.thustheframerat eslows downtobethedesiredvalue. note: lfra mustbeanumbergreaterthan4. theadjustedframeratefor1and4bitmodescan be foundinthefollowingequations 1-bit mode lymax lfra lxmax lcdck rate frame ? + + ? = )5.1 ( 16 equation141 4-bit mode lymax lfra lxmax lcdck rate frame ? + + ? = )5.1 ( 4 equation142 16.4.8 lcd frame rate adjust register address name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 def ault $049 lfra w fra[5] fra[4] fra[3] fra[2] fra[1] fra[0] 000000 bit5~0: lfra[5:0] :extendedtimeofeachscanline 16.4.9 lcd ac signal rate register thelcdalternatingsignalrateregister( lac )specifiesthetimeofhorizontallinesthealtern atingsignaltoggles. table 16-8 lcd ac signal rate register address name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 def ault $04a lac r/w ac[4] ac[3] ac[2] ac[1] ac[0] 00000 bit2~0: ac[4:0] :timeofhorizontallinestheacsignaltoggles ac[4:0] acsignal 00000 everyframe 00001 every3lines 00010 every5lines 00011 every7lines : : 11101 every59lines 11110 every61lines 11111 every63lines 16.4.10 lcd pwm contrast control register theST2202Achievescontrastcontrolfunctionbyou tputtingapwmsignalfrom blank .thedutyratioofpwmsignal,also isthecontrastlevel,iscontrolledby lpwm[5:0] with64steps. table 16-9 lcd pwm contrast control register address name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 def ault $04b lpwm r/w lpwm[5] lpwm[4] lpwm[3] lpwm[2] lpwm[1] lpwm[0] 000000 bit5~0: lpwm[5~0] : lcdcontrastcontrol lpwm[5:0] contrastlevel 00000 64(maximum) 00001 63 00010 62 : : 11101 3 11110 2 11111 1(minimum)
ST2202A ver2.5 46 / 75 9/16/2008 1 1 7 7 . . s s e e r r i i a a l l p p e e r r i i p p h h e e r r a a l l i i n n t t e e r r f f a a c c e e thest2202containsoneserialperipheralinterface (spi) moduletointerfacewithexternaldevices,suchas flash memory,analogtodigitalconverter,andotherperi pherals, includinganotherst2202.thespiconsistsofamas teror slaveconfigurableinterfacesothatconnectionsof both masterandslavedevicesareallowable.fivesignal s multiplexedwithportcareusedbyspi.withequip ped data_ready and ss (slaveselect)controlsignalsand transmit/receivebuffers,fasterdataexchangewith fewer softwareinterruptsiseasytobemade.datalength is widelysupportedfrom7bitupto16bittosatisfy various applications.oneclockgeneratorisprovidedfort he synchronouscommunicationclocksck,whichissourc ed fromosck. figure171illustratestheblockdiagramof spi. cpuinterface clock generator 16bitshiftregister (msbfirst) 16bittransmit buffer 16bitreceive buffer mosi miso interface control sck osck data_ready spick ss figure 17-1 spi block diagram 17.1 spi operations thespicontainsone16bitshiftregisterandtwo 16bit buffersfortransmissionandreceivingrespectively .data withvariablelengthfrom7bitto16bitcanbeex changed withexternaldevicesthroughtwodatalines.data lengthis controlledbybitcountregister bc[3:0] (bit3~0ofspiclock controlregister sckr) .thecurrentexchangewillbeover whiletheexchangedbitnumberreachesbitcountse tting. thesynchronouscommunicationclocksckisusedto synchronizetwodevicesandtransferdatainandou tofthe shiftregister.dataisclockedbysckwithaprogr ammable datarate,whichisassignedby sck[2:0] (bit6~4ofspi clockcontrolregister sckr ).referto table117forall clockratesettings. thespiblockiscontrolledby spien ( sctr[7] ).setting spien willenablespifunctionandtheclockdivider.th en theinternalstatesofspiwillberesettoinitial values.after that,writedatato sdatal willinitiateanexchange.while exchanging,thebusyflagwillbesetandisreport edin sbz (bit4ofspistatusregister ssr ). aslaveselectsignal ss (multiplexedwithpc4)isusedto identifyindividualselectionofaslavespidevice .slave devicesthatarenotselecteddonotinterferewith spibus activities.foramasterspidevice, ss canbeusedto indicateamultiplemasterbuscontentionwhichcan be reportedinmodefaultbit mderr (bit3ofspistatus register ssr ). 17.1.1 clock phase and polarity controls fourcombinationsofserialclock(sck)phaseandp olarity areselectablebytwocontrolbits pha and pol (bit2~1of spicontrolregister sctr ). figure172and figure 173showthetransmissionformatoftwophasesett ings. note: theclocksettingsshouldbeidenticalfor masterandthecommunicatingslavedevice. transmission format C pha = 0 inthismode,bothmasterandthecommunicatingsla ve shouldpresentmsbafterthefallingedgeof ss .thenthe firstedgeofsckwillbethefirstcapturestrobe ofinput data.if pol =0,thisfirstedgeisrisingedge;if pol =1,itwill beafallingedge. transmission format C pha = 1 inthismode,bothmasterandthecommunicatingsla vewill bereadyafterthefallingedgeof ss .thetwooutputmsb atthefirstedgeofsck.thenthesecondedgewill bethe capturestrobe.if pol =0,thefirstedgeisrisingedge;if pol =1,itwillbeafallingone.
ST2202A ver2.5 47 / 75 9/16/2008 msb bit6 bit5 bit4 bit3 bit2 bit1 lsb msb bit6 bit5 bit4 bit3 bit2 bit1 lsb pol=0 pol=1 outputfrommaster (mosi) frommaster outputfromslave (miso) ss figure 17-2 transmission format (pha = 0) msb bit6 bit5 bit4 bit3 bit2 bit1 lsb msb bit6 bit5 bit4 bit3 bit2 bit1 lsb pol=0 pol=1 outputfrommaster (mosi) frommaster outputfromslave (miso) ss figure 17-3 transmission format (pha = 1) 17.1.2 transmit buffer and receive buffer operationsoftransmitandreceivebuffersaredisc ussed below. transmit buffer thetransmitbufferis16bitlong,andiswriteon ly.this bufferisemptyafterthespiwasenabledatthebe ginning. inthemeantime,thetransmitbufferemptyflag txemp ( ssr[5] )willbesettoindicatethestatusofbuffer.up to16 bitsofdatacanbefilledwithwritestospidata registers ( sdatal and sdatah ). txemp willbeclearedafter sdatal iswroteavalue(writing sdatah willnotaffect txemp ).oncetheshiftregisterproceedstoexchange, datainbufferwillbeloadedintoshiftregistera nd txemp willbesetagain.meanwhileaspitransmitterinte rruptwill beissuedandthetransmitbuffercanbefilledwit hnew datafornexttransmission. receive buffer thereceivebufferis16bitlong,andisreadonly .this bufferisemptyafterthespiwasenabledfirst.in the meantime,thereceivebufferreadyflag rxrdy ( ssr[6] ) willbeclearedtoindicatestatusofbuffer.twob ytesofdata canbereadfrom sdatal and sdatah .aftercompleting exchange,datainshiftregisterwillbeloadedint oreceive buffer,andthen rxrdy willbesettoindicatethatthe receiveddataisavailable.next, rxrdy shouldbecleared byonereadinstructionto sdatal (reading sdatah will notaffect rxrdy) .incaseofmastermode,ifone completeddataismovingintoreceivebufferand rxrdy is stillset,themovingactivitywillnostopbutthe receive bufferoverrunflag oerr ( ssr[1] )willbesettoindicate thatanolddataisoverwrote.ifitisinslavemo de,the receivebufferwillnotbeoverwrotewhile oerr equals1. oerr canbeclearedbyreading sdatal orbyanywrite to ssr . 17.1.3 master, slave modes and the shift register thespicanoperateinmasterorslavemodeaccordi ngto smod ( sctr[0] ).thesetwomodesandoperationsofthe shiftregisterforeacharediscussedbelow. master mode thespioperatesasamasterdevicewhensetting smod . inthismode,communicationclockisprovidedbyst 2202 withsck(pc1).iftheremayhavemorethanonemas ter connected,buscontentioncanbedetectedbysettin gmode faultdetectionbit meren ( sctr[4] ). ss signalshouldbe inputandpulledhightemporarilyduringthisdetec tion. once ss inputslowlevel,amodefaultstatuscanbe reportedat mderr ( ssr[2] ). somespideviceshave data_ready outputtosuspend theincomingtransmission.setting srdy ( pfc[5] )may includetimingof data_ready ,whileclearingthisbitto discardit.communicationclockanddatatransmissi ononly startsafter data_ready returnstolowlevel.theactive levelof data_ready canbeinvertedtobehighlevel activebysettinginversioncontrolbit drinv ( sctr[3] ). whentransmission,datainshiftregisterwillbes hiftedto
ST2202A ver2.5 48 / 75 9/16/2008 masterdataoutputmosi(pc3)withmostsignificant bit (msb)first,whiledatafromserialdatainputmiso (pc2) willbeshiftedinaswell.aftertheexchangedbit sreachbit countsetting,currentdataiscompleteandthenmo vesto receivebuffer. theexchangecontinueswithautoreloadfunctionof shift registerif txemp iscleared.thatis,msbofnextdatawill besentoutandbereceivedinrightafterthelsb ofthe previousonewithnopause. aftertheexchangewastriggered,theslaveselect signal ss (pc4)outputslowleveltoenabletheexternalsla ve device.itkeepsatlowlevelduringexchangesofd ataand data,andreturnstohighwhenexchangescease. slave mode inslavemode, ss (pc5)andsck(pc1)becomeinput, while data_ready (pc5)isnotfunctional.theexchange takesplaceonlywhen ss inputslowlevelandendswhen itreturnstohigh.onthefallingedgeof ss ,theshift registerwillbeloadedwithdataintransmitbuffe r,andthen theexchangeinitiates.duringexchanging,datais clocked byexternalclockfromsckandisshiftedinandou tthe shiftregister.exchangeddatawillbereadywhent he exchangedbitnumbermatchesbitcountsetting.aft erdata isready,datatransferbetweenshiftregisterand twobuffers willfunctionautomaticallyasitdoesinmastermo de.so thattheshiftregistercanbereadyforthesuccee dingclock edge.if ss risesbeforeenoughdatabits,current exchangeisoveranyway,butthebitcountviolatio nflag berr ( ssr[0] )willbeset. 17.1.4 spi interrupts fourinterruptsaresupportedbyspiwithtwointer rupt vectors. transmitbufferemptyinterrupthappenswhenadata exchangestartsandthetransmitbufferisempty.t his statuscanbereadfromstatusbit txemp ( ssr[5] ). receivebufferreadyinterrupthappenswhenadata exchangecompletesandthereceivebufferisfilled withone newdata.thisinterruptisenabledbysettingcont rolbit rxien ( sctr[6] ).thestatusisreportedatstatusbit rxrdy ( ssr[6] ). theothertwointerruptsareerrorinterruptsanda reboth enabledbycontrolbit erien ( sctr[5] ).receivebuffer overruninterruptandbitcountviolationinterrupt sharethe interruptvectorwithreceivebufferreadyinterrup t.these threeinterruptsareortogethertogenerateani ndividual vector.inmastermode,receivebufferoverruninte rrupt happenswhenmovingnewdatafromshiftregisterto receivebufferwith rxrdy equals1.theoverruninterrupt isissuedandthestatusbit oerr ( ssr[1] )willbeset.in slavemode,olddatainreceivebufferwillnotbe flushed whileotheroperationsarethesamewiththoseinm aster mode. bitcountviolationinterruptonlyhappensinslave mode.if ss inputrisesbeforeenoughdatabitsarereached, currentexchangeisoveranyway,butthebitcount violation flag berr ( ssr[0] )willbesetandtheinterruptisissued. 17.2 interface signals fivemultiplexedsignalsareusedtointerfacewith otherspi devices.withsettingrelatedbitsofportfunction select register pfc ,thesesignalscanbeactivated.directionand functionselectbitsshouldbeascertainedbeforet heyare used.refertosection 9forthesesettings. sck (pc1) thisisabidirectionalspisynchronousclocki/o, whichis multiplexedwithpc1.sckisoutputinmastermode and inputinslavemode. miso (pc2) masterin/slaveoutbidirectionalsignal,whichis multiplexedwithpc2.externaldataisinputtedto thispinto theshiftregisterinmastermode.inslavemode,i tisan outputofshiftregister. mosi (pc3) masterout/slaveinbidirectionalsignal,whichis multiplexedwithpc3.datainshiftregisterisout puttedfrom thispininmastermode.inslavemode,itisanin putof externaldatatotheshiftregister. ss (pc4) ss isabidirectionalslaveselectsignal,whichis multiplexedwithpc4.inmastermode, ss isoutputto enableaslavedevice.inslavemode, ss isinputtedalow leveltotriggertheexchange. data_ready (pc5) data_ready isaninputsignal,whichismultiplexedwith pc5.itisusedonlyinmastermodeandcanbeagp ioin slavemode.theoperationof data_ready canbe enabledbysetting pfc[5] .thedefaultactivelevelishigh, andcanbeinvertedbysetting drinv ( sctr[3] ).active levelisinputtedtoindicatethatthecommunicatin gslaveis readyfordataexchange.
ST2202A ver2.5 49 / 75 9/16/2008 17.3 spi control/status registers spicontrolandstatusregistersaresummarizedin table171. table 17-2 summary of spi control registers address name r/w bit 7/15 bit 6/14 bit 5/13 bit 4/12 bit 3/11 bit 2/10 bit 1/9 bit 0/8 default $050 sdatal r/w sd[7] sd[6] sd[5] sd[4] sd[3] sd[2] sd[1] sd[0] ???????? $051 sdatah r/w sd[15] sd[14] sd[13] sd[12] sd[11] sd[10] sd[9] sd[8] ???????? $052 sctr r/w spien rxien erien meren drinv pol pha smod 00000000 $053 sckr r/w sck[2] sck[1] sck[0] bc[3] bc[2] bc[1] bc[0] 0000000 r rxrdy txemp sbz mderr oerr bcerr 000000 $054 ssr w writeanyvaluetoresetssr $00a pcc r/w pcc[7] pcc[6] pcc[5] pcc[4] pcc[3] pcc[2] pcc[1] pcc[0] 00000000 $00d pfc r/w rxd0 txd0 srdy ss mosi miso sck intx 00000000 $03d ireqh r/w irurx irutx irsrx irstx 0000 $03f ienah r/w ieurx ieutx iesrx iestx 0000 17.3.1 spi data registers table 17-3 spi data registers address name r/w bit 7/15 bit 6/14 bit 5/13 bit 4/12 bit 3/11 bit 2/10 bit 1/9 bit 0/8 default $050 sdatal r/w sd[7] sd[6] sd[5] sd[4] sd[3] sd[2] sd[1] sd[0] 000 00000 $051 sdatah r/w sd[15] sd[14] sd[13] sd[12] sd[11] sd[10] sd[9] sd[8] 00000000 bit 7~0: write :writelowbytedatatotransmitbuffer/clearst atusbit txemp /triggerandataexchange read :readlowbytedatafromreceivebuffer/clearst atusbit rxrdy bit15~8: write :writehighbytedatatotransmitbuffer/ read :readhighbytedatafromreceivebuffer 17.3.2 spi control register table 17-4 spi control register address name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 def ault $052 sctr r/w spien rxien erien meren drinv pol pha smod 00000000 bit7: spien : spicontrolbit 0 =spidisable 1=spienable bit6: rxien : receivebufferreadyinterruptcontrolbit 0 =receivebufferreadyinterruptdisable 1=receivebufferreadyinterruptenable bit5: erien : twoerrorinterruptscontrolbit 0 =twoerrorinterruptsdisable 1=twoerrorinterruptsenable bit4: meren : modefaultdetectioncontrolbit 0 =modefaultdetectiondisable 1=modefaultdetectionenable bit3: drinv : data_ready activelevelselectionbit 0 =activelevelishigh 1=activelevelislow bit2~1: spha/spol : spiclockpolarityandphasecontrolbits refertosection 17.1.1 bit0: smod : master/slavemodesselectionbit 0 =selectslavemode 1=selectmastermode
ST2202A ver2.5 50 / 75 9/16/2008 17.3.3 spi status register table 17-5 spi status register address name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 def ault r rxrdy txemp sbz mderr oerr bcerr 000000 $054 ssr w writeanyvaluetoresetssr bit6: rxrdy : receivebufferstatusflag 0 =receivebufferisempty 1=receivebufferisfilledwithnewdataandisr eady bit5: txemp : transmitbufferstatusflag 0 =dataintransmitbufferiswaitingforexchangin g 1=transmitbufferisempty bit4: sbz : spibusyflag 0 =spiisidle 1=spiisbusyexchangingdata bit2: mderr : modefaultstatusflag 0 = ss signalisathighlevelandisnormal 1= ss signalinputslowlevel/amodefaultstatusdete cted bit1: oerr : receivebufferoverrunerrorflag 0 =noreceivebufferoverrunerror 1=receivebufferoverrunerroroccurs bit0: berr : bitcountviolationflag 0 =exchangeddatabitnumbermatchesbitcountsett inginslavemode 1=exchangeddatabitnumberislessthanbitcoun tsettinginslavemode
ST2202A ver2.5 51 / 75 9/16/2008 1 1 8 8 . . u u n n i i v v e e r r s s a a l l a a s s y y n n c c h h r r o o n n o o u u s s r r e e c c e e i i v v e e r r / / t t r r a a n n s s m m i i t t t t e e r r thest2202integratesoneuniversalasynchronous receiver/transmitter(uart),whichcanbeusedto communicatewithexternalserialdevices.serialda tais transmittedandreceivedatstandardbitratesusin gthe internalbaudrategenerator(bgr),whichiscontro lledby bgrcontrolregister bctr .settingsofclockoutputof bgr(bgrck)canbefoundinsection 11. figure181 showstheblockdiagramofuart.summaryofuart controlregistersislistedin table181. cpuinterface baudrate generator transmitter receiver txd0 rxd0 serial interface irda interface txd1 rxd1 figure 18-1 uart block diagram table 18-1 summary of uart control registers address name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 def ault $060 uctr r/w pen pmod umod brk 0000 r fer per oer rxbz rxen txbz txen 0000000 $061 ustr w rxtrg rxen txtrg txen 0000 $062 irctr r/w rxinv txinv pw1 pw0 iren 00000 $063 bctr r/w test bstr bmod bgren 0000 $064 udata r/w ud[7] ud[6] ud[5] ud[4] ud[3] ud[2] ud[1] ud[0] ???????? $066 brs r/w brs[7] brs[6] brs[5] brs[4] brs[3] brs[2] brs[1] brs[0] ???????? $067 bdiv r/w bdiv[7] bdiv[6] bdiv[5] bdiv[4] bdiv[3] bdiv[2] bdiv[1] bdiv[0] ???????? $00a pcc r/w pcc[7] pcc[6] pcc[5] pcc[4] pcc[3] pcc[2] pcc[1] pcc[0] 00000000 $00b pcd r/w pcd[7] pcd[6] pcd[5] pcd[4] pcd[3] pcd[2] pcd[1] pcd[0] 00000000 $00d pfc r/w rxd0 txd0 srdy ss mosi miso sck intx 00000000 $00e pfd r/w rxd1 txd1 cs6 cs5 cs4 cs3 cs2 cs1 00000000 $03d ireqh r/w irurx irutx irsrx irstx 0000 $03f ienah r/w ieurx ieutx iesrx iestx 0000 18.2 uart operations theuarthastwomodesofoperation,nrzandirda, whichrepresentdataindifferentwaysforserial communicationprotocols,rs232andirda. 18.2.1 nrz mode thenonreturntozero(nrz)modeisprimarilyasso ciated withrs232.eachcharacteristransmittedasafra me delimitedbyastartbitatthebeginningandasto pbitatthe end.databitsaretransmittedleastsignificantbi t(lsb)first, andeachbitoccupiesaperiodoftimeequalto1f ullbit.if parityisused,theparitybitistransmittedafter themost significantbit.datasettingsincludingdatalengt h,stopbit numberandparityarecontrolledbybitfieldsin uctr . figure182illustratesacharactersinnrzmode . 18.2.2 irda mode irdamodeusescharacterframesasnrzmodedoes,b ut, insteadofdrivingonesandzerosforafullbitti meperiod, zerosaretransmittedasthreesixteenth(orless) bittime pulses(whichisselectedby pw[1:0] ( irctr[2:1] ),and onesremainlow.thepolarityoftransmittedpulses and expectedreceivepulsescanbeinvertedsothatad irect connectioncanbemadetoexternalirdatransceiver modulesthatuseactivelowpulses.thisiscontrol ledby rxinv and txinv ( irctr[7:6] ).irdamodeisenabledby controlbit iren ( irctr[0] ). figure183illustratesa charactersinirdamode.
ST2202A ver2.5 52 / 75 9/16/2008 bit0 startbit 1 23 4 5 6 bit7 paritybit stopbit figure 18-2 nrz ascii s with odd parity bit0 startbit 1 23 4 5 6 bit7 paritybit stopbit figure 18-3 irda ascii s with odd parity twokindsofcharacter,7bitand8bit,aresuppor tedby st2202.thisiscontrolledbymodeselectionbit umod ( uctr[1] ).parityoptionsarecontrolledbyparityenableb it pen ( uctr[3] )andparitymodeselectionbit pmod ( uctr[2] ).otheroperationsfortransmitterandreceiver aredescribedbelow. 18.2.3 transmitter operation transmitteroperationiscontrolledbycontrolbit txen ( ustr[0] ).thetransmitteracceptsacharacterfromthe cpubus,andthentransmitsitimmediatelyaftertr iggered bywriting1tocontrolbit txtrg ( ustr[1] ).whena characterisavailablefortransmission,thestart, stop,and parity(ifenabled)bitsareaddedintothecharact er,and thenitisseriallyshifted(lsbfirst)atthesele ctedbitrate. whiletransmitterisbusy,thebusystatusisrepor tedat txbz ( ustr[1] )withlogicvalue1.afteralldatabitsare finished, irutx ( ireq[10] )willbesettoissuetheinterrupt request.nextdatatransmissionmaycontinuewiths etting triggerbit txtrg again. ifthetransmitbufferisempty,thetransmitterou tputsa continuousidle(whichis1fornormalpolarity). moreover acontinuous0canalsobeoutputtedasabreakc haracter bysetting brk bit( uctr[0] )andthensetthetriggerbit. . 18.2.4 receiver operation receiveroperationiscontrolledbycontrolbit rxen ( ustr[2] ).oncethereceiverisenabled,itsearchesfora startbit,qualifiesit,andthensamplesthesucce edingdata bitsattheperceivedbitcenter.jittertolerance andnoise immunityareprovidedbysampling16timesperbit and usingavotingcircuittoenhancesampling.whiler eceiving, thebusystatusofreceivercanbereadfrom rxbz ( ustr[3] )withlogiclevel1. receivingactivitywillbecompleteafterthestop bitis detected.then irurx ( ireq[11] )willbesettoissuethe interruptrequest.thereceiveddatacanbeobtaine dby readingdataregister udata .thenthereceivetriggerbit rxtrg ( ustr[3] )shouldbesettoindicatethatthedata registercanbeoverwrotenexttime. threekindsoferrorsmayarisefromillegalreceiv eddata, whicharereportedat3bitsofstatusregister ustr[6:4] andarediscussedbelow. 1. buffer overrun error thiserrorindicatesthatthereceivetriggerbitw asnotset andthereceiveroverwrotedatainreceivebuffer, i.e.,the previouscharacterwaslost.thisalsomeanstheso ftware isnotkeepingupwiththeincomingdatarate.erro ris updatedandreportedbyreading oer ( ustr[4] )for currentreceivedcharacter. 2. parity error ifparityisenabled,theparitybitofcurrentrec eived characterischeckedandthestatusisupdatedinr egister bit per ( ustr[5] ). 3. framing error thiserrorindicatesthataframingerrorisdetect edand theremaybecorrupteddatawithmissingstopbit. erroris updatedandreportedbyreading fer ( ustr[6] )forcurrent receivedcharacter. 18.3 interface signals twosetsofdatalinescanbeenabledsimultaneousl yfor communication,txd0(pc6),rxd0(pc7)andtheauxilia ry pinstxd1(pd6),rxd1(pd7).datacaninputsandoutp uts fromandtothesepins.withsettingrelatedbitso fport functionselectregisters( pfc and pfd ),signalsofthe externaldevicescanbeconnected.datainandfrom these communicationi/oscanbeinvertedbysettingpolar ity controlbit rxinv and txinv ( irctr[7:6] ).direction settingsandfunctionselectbitsshouldbeascerta ined beforeusingsignals.refertosection 9forthesesettings. txd0 (pc6)/txd1 (pd6) theuarttransmitdatasignalisoutputtooneorb othof thesetwopins,whicharemultiplexedwithpc6and pd6. thesepinsconnecttostandardrs232orinfrared transceivermodules. rxd0 (pc7)/rxd1 (pd7) theuartreceivedatasignalisinputfromoneorb othof thesetwopins,whicharemultiplexedwithpc7and pd7.if rxd0andrxd1areenabledatatime,bothsignalsw illbe gatedwithandlogictoproduceonesinglesignal. these
ST2202A ver2.5 53 / 75 9/16/2008 pinsalsointerfacetostandardrs232andinfrared transceivermodules. 18.4 uart control/status registers 18.4.1 uart control register table 18-2 uart control register address name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 def ault $060 uctr r/w pen pmod umod brk 0000 bit3: pen : paritycontrolbit 0 =disableparity 1=enableparity bit2: pmod : paritymodeselectionbit 0 =evenparity 1=oddparity bit1: umod : 7/8bitmodeselectionbit 0 =7bitmode(thereceiveddatabit7willbeset tozero) 1=8bitmode bit0: brk : breakcharacter 0 =normalcharacter 1=transmitbreakcharacter 18.4.2 uart status control register table 18-3 uart status control register address name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 def ault r fer per oer rxbz rxen txbz txen 0000000 $061 ustr w rxtrg rxen txtrg txen 0000 bit6: fer : receiveddataframeerrorstatusbit 0 =currentreceiveddataisnormal 1=frameerroroccurs bit5: per : parityerrorstatusbit 0 =currentreceiveddataisnormal 1=parityerroroccurs bit4: oer : overrunerrorstatusbit 0 =currentreceiveddataisnormal 1=overrunoccurs bit3: rxbz : receiverbusybit 0 =receiverisnotbusy 1=receiverisbusy bit2: rxen : receivercontrolbit 0 =receiverisdisabled 1=receiverisenabled bit1: txbz : transmitterbusybit 0 =transmitterisnotbusy 1=transmitterisbusy bit0: txen : transmittercontrolbit 0 =transmitterisdisabled 1=transmitterisenabled bit3: rxtrg : receivertriggerbit writing1tomakereceivertobereadyfornext data bit1: txtrg : transmittertriggerbit writing1totriggerthetransmittertostart transmission
ST2202A ver2.5 54 / 75 9/16/2008 18.4.3 irda control register table 18-4 irda control register address name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 def ault $062 irctr r/w rxinv txinv pw1 pw0 iren 00000 bit7: rxinv : receivedatainversionbit 0 =receivedataisnormal 1=receivedataisinverted bit6: txinv : transmitdatainversionbit 0 =transmitdataisnormal 1=transmitdataisinverted bit2~1: pw[1:0] : irdapulsewidthselectionbits pw[1:0] pulsewidth 00 1/16 01 2/16 1x 3/16 bit0: iren : irdamodecontrolbit 0 =normalmode(nrz) 1=irdamode 18.4.4 uart data register table 18-5 uart data register address name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 def ault $064 udata r/w ud[7] ud[6] ud[5] ud[4] ud[3] ud[2] ud[1] ud[0] ??? ????? write :writecharacterdatatotransmitter/ read :readcharacterdatafromreceiver
ST2202A ver2.5 55 / 75 9/16/2008 18.5 settings for standard baud rates oneclockof16timesofthecommunicationbaudrat eis neededbytheuarttoperformdatatransmission/rec eiving, synchronization,andparity/erroroperations.setti ngsof brs , bdiv ,andosckranges forstandardbaudratesare listedin table186.besides,finemodulationmodeand fullmodulationstrengtharesuggestedwhenusingb grto generateclockforuart.storevalueof$03to bctr to selectthesetwooptions. table 18-6 settings for standard baud rates osck (mhz) osck (mhz) baud rate brs bdiv max. min. error (%) baud rate brs bdiv max. min. error (%) 19 65 1.33 1.16 0.23 19 2 1.33 1.16 1.33 21 72 1.47 1.28 0.44 27 3 1.89 1.65 4.00 23 82 1.68 1.46 0.10 28 3 1.96 1.71 0.44 27 92 1.89 1.65 0.17 29 3 2.03 1.77 3.11 30 102 2.10 1.83 0.39 36 4 2.52 2.19 4.00 34 116 2.38 2.07 0.05 37 4 2.60 2.26 1.33 37 126 2.60 2.26 0.23 38 4 2.66 2.32 1.33 42 143 2.95 2.56 0.05 39 4 2.74 2.38 4.00 47 106 3.30 2.86 0.27 45 5 3.16 2.74 4.00 49 167 3.44 2.99 0.15 47 5 3.30 2.86 0.2 7 55 188 3.86 3.35 0.14 49 5 3.44 2.99 4.53 61 208 4.28 3.72 0.10 54 6 3.79 3.29 4.00 600 68 232 4.77 4.14 0.05 55 6 3.86 3.35 2.22 19 32 1.33 1.16 1.33 56 6 3.93 3.41 0.44 21 36 1.47 1.28 0.44 57 6 4.00 3.47 1.33 24 41 1.68 1.46 0.10 58 6 4.07 3.54 3.11 27 46 1.89 1.65 0.17 59 6 4.14 3.60 4.89 30 51 2.10 1.83 0.39 63 7 4.42 3.84 4.00 33 58 2.38 2.07 0.05 64 7 4.49 3.90 2.48 37 63 2.60 2.26 0.23 65 7 4.56 3.96 0.95 42 72 2.95 2.56 0.44 19200 66 7 4.63 4.02 0.57 47 80 3.30 2.86 0.27 27 2 1.89 1.65 4.00 49 84 3.44 2.99 0.44 28 2 1.96 1.71 0.44 55 94 3.86 3.35 0.14 29 2 2.03 1.77 3.11 61 104 4.28 3.72 0.10 41 3 2.88 2.50 2.81 1200 68 116 4.77 4.14 0.05 42 3 2.95 2.56 0.44 19 16 1.33 1.16 1.33 44 3 3.09 2.68 4.30 21 18 1.47 1.28 0.44 54 4 3.79 3.29 4.00 23 20 1.61 1.40 1.87 55 4 3.86 3.35 2.22 26 22 1.82 1.59 0.85 56 4 3.93 3.41 0.44 29 25 2.03 1.77 1.01 57 4 4.00 3.47 1.33 33 28 2.31 2.01 0.57 58 4 4.07 3.54 3.11 37 32 2.60 2.26 1.33 59 4 4.14 3.60 4.89 42 36 2.95 2.56 0.44 67 5 4.70 4.08 4.71 47 40 3.30 2.86 0.27 68 5 4.77 4.14 3.29 49 42 3.44 2.99 0.44 28800 69 5 4.84 4.21 1.87 55 47 3.86 3.35 0.14 19 1 1.33 1.16 1.33 61 52 4.28 3.72 0.10 36 2 2.52 2.19 4.00 2400 68 58 4.77 4.14 0.05 37 2 2.59 2.25 1.33 19 8 1.33 1.16 1.33 39 2 2.74 2.38 4.00 21 9 1.47 1.28 0.44 54 3 3.79 3.29 4.00 23 10 1.61 1.40 1.87 55 3 3.86 3.35 2.22 26 11 1.82 1.59 0.85 56 3 3.93 3.41 0.44 29 12 2.03 1.77 3.11 57 3 4.00 3.47 1.33 33 14 2.31 2.01 0.57 58 3 4.07 3.54 3.11 37 16 2.60 2.26 1.33 59 3 4.14 3.60 4.89 4800 42 18 2.95 2.56 0.44 38400 72 4 5.05 4.39 4.00
ST2202A ver2.5 56 / 75 9/16/2008 47 20 3.30 2.86 0.27 27 1 1.89 1.65 4.00 51 22 3.58 3.11 1.09 28 1 1.96 1.71 0.44 56 24 3.93 3.41 0.44 29 1 2.03 1.77 3.11 61 26 4.28 3.72 0.10 54 2 3.79 3.29 4.00 68 29 4.77 4.14 0.05 55 2 3.86 3.35 2.22 19 4 1.33 1.16 1.33 56 2 3.93 3.41 0.44 23 5 1.61 1.40 1.87 57 2 4.00 3.47 1.33 24 5 1.68 1.46 2.40 58 2 4.07 3.54 3.11 27 6 1.89 1.65 4.00 57600 59 2 4.14 3.60 4.89 28 6 1.96 1.71 0.44 54 1 3.79 3.29 4.00 29 6 2.03 1.77 3.11 55 1 3.86 3.35 2.22 33 7 2.31 2.01 0.57 56 1 3.93 3.41 0.44 37 8 2.60 2.26 1.33 57 1 4.00 3.47 1.33 42 9 2.95 2.56 0.44 58 1 4.07 3.54 3.11 47 10 3.30 2.86 0.27 115200 59 1 4.14 3.60 4.89 51 11 3.58 3.11 1.09 56 12 3.93 3.41 0.44 61 13 4.28 3.72 0.10 9600 66 14 4.63 4.02 0.57 example: in case of baud rate=115200, brs=58, and bdiv=1, th e osck must be in the range of 4.07 to 3.54mhz.
ST2202A ver2.5 57 / 75 9/16/2008 1 1 9 9 . . d d i i r r e e c c t t m m e e m m o o r r y y a a c c c c e e s s s s ( ( d d m m a a ) ) tospeedupthememoryaccessofthissystem,a sequentialdirectmemoryaccess(dma)controlleris designedin.dmacanperformmemorytransferfuncti on moreefficientthancpudoes.whiledmaworking,da ta romregister(drr)willdisableanddmausedma memorybankregister(dmr)toaccessrom.afterdma complete,rombankcontrolstillreturntodrr. withthehelpofdmrcanmakedmsacrossbank boundarysmoothly,butdmrisonlyvalidfordms. the dmr can automatic increases when dms across bank boundary. note:locationofsourcedatacannotfallinther ange ofinternalsram(thatistherangeof 0100h~fffh). lcd dma cpu sram rom lcd_ctl figure 19-1 system block diagram 19.1 dma control register thecontrolregisterisshownasfollowing: table 19-2 dma control register (lctl) address name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 def ault $028 dmsl w dms[7] dms[6] dms[5] dms[4] dms[3] dms[2] dms[1] dms[0] ???????? $029 dmsh w dms[15] dms[14] dms[13] dms[12] dms[11] dms[10] dms[9] dms[8] ???????? $02a dmdl w dmd[7] dmd[6] dmd[5] dmd[4] dmd[3] dmd[2] dmd[1] dmd[0] ???????? $02b dmdh w dmd[15] dmd[14] dmd[13] dmd[12] dmd[11] dmd[10] dmd[9] dmd[8] ???????? $02c dcntl w dcnt[7] dcnt[6] dcnt[5] dcnt[4] dcnt[3] dcnt[2] dcnt[1] dcnt[0] ???????? $02d dcnth w dmam dcnt[11] dcnt[10] dcnt[9] dcnt[8] ????? $036 dmrl r/w dmr[7] dmr[6] dmr[5] dmr[4] dmr[3] dmr[2] dmr[1] dmr[0] 00000000 $037 dmrh r/w dmr[10] dmr[9] dmr[8] 000 dms[15:0] : dmasourcedatastartingaddressregister dmd[15:0]: dmadestinationdatastartingaddressregister dcnt[11:0]: dmamovingdatabytecounterregister dmr[10:0]: dmasourcedatabankregister( dmr worksonlywhen dms isintherangefrom8000htoffffh). dmam ( dcnth[4] ) : dmadestinationaddressincreasingmodeselection bit 0=destinationaddressincreasesautomatically. 1=destinationaddressisfixed. thedmaalwaysmove(dcnt+1)bytesofdata.dmawil l startrightaftercpuwritedataintoregisterdcnt l.during thedmaoperation,thecpuhold,untilthedmatran sfer completed.thedmrregisterresetto$00onreal chip, butemulationboardisunknown,sorecommendinit ial dmrregisterbeforeuse. before read/write you have to initial the prr, drr, dmr register when system rese t.
ST2202A ver2.5 58 / 75 9/16/2008 19.2 dma programming flow (dmsh,l):=dmasourceaddress (dmdh,l):=dmadestinationaddress dcnth:=numberofbytes dmastart cpuhold dmr:=dmamemorybankregister dcntl:=numberofbytes figure 19-2 dma programming flow 19.3 example program 1: thisprogramfills00toaddress$1000~$12ff. stz $1000 ;;00to$1000 stz ST2202A ver2.5 59 / 75 9/16/2008 19.4 example program 2: thisprogrammovesdatainaddress$1080~$12ffto$ 1000~$127f. lda #$80 sta ST2202A ver2.5 60 / 75 9/16/2008 2 2 0 0 . . p p o o w w e e r r d d o o w w n n m m o o d d e e s s st2202hasthreepowerdownmodes:wai0,wai1and stp.theinstructionwaiwillenableeitherwai0o rwai1, whichiscontrolledby wait ( f[2] ).andtheinstructionstp willenable stp modeinthesamemanner.wai0and wai1modescanbewakedupbyinterrupt.however, stp modecanonlybewakedupbyhardwarereset. table 20-1 system control register (sys) address name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default r xsel ostp xstp wskp wait irren high 00000001 $030 sys w xsel ostp xstp wskp wait irren lvden 00000000 bit2: wait : wai0/wai1modeselectbit 0 =waiinstructioncausesthechiptoenterwai0m ode 1=waiinstructioncausesthechiptoenterwai1 mode 20.1 wai-0 mode: if wait iscleared,waiinstructionmakesmcuenterwai0 mode.inthemeantime,theoscillator,interrupts, timer/counter,andpsgarestillworking.ontheot herhand cpuandtherelatedinstructionexecutionstop.all registers, ram,andi/opinswillretainthesamestatesasth ose beforethemcuenteredpowerdownmode.wai0mode canbewakedupbyresetorinterruptrequesteven ifuser setsinterruptdisableflag i .inthatcasemcuwillbewaked upbutnotenteringinterruptserviceroutine.ifi nterrupt disableflagiscleared( i =0),thecorrespondinginterrupt vectorwillbefetchedandtheserviceroutinewill be executed.thesampleprogramisshownbelow: lda #$00 sta ST2202A ver2.5 61 / 75 9/16/2008 figure 20-1 status under power down modes sysck source is osc: mode timer0,1 sysck lcd osc oscx base timer ram reg. i/o wake-up condition wai-0 retain reset,anyinterrupt wai-1 stop stop stop stop retain reset,anyinterrupt stp stop stop stop stop retain reset sysck source is oscx: mode timer0,1 sysck osc oscx base timer ram reg. i/o lcd wake-up condition wai-0 retain wrongframe reset,anyinterrupt wai-1 stop stop retain stop reset,anyinterrupt stp stop stop retain stop reset
ST2202A ver2.5 62 / 75 9/16/2008 2 2 1 1 . . w w a a t t c c h h d d o o g g t t i i m m e e r r thewatchdogtimer(wdt)isanaddedcheckthata programisrunningandsequencingproperly.whenth e applicationsoftwareisrunning,itisresponsible forkeeping the2or8secondwatchdogtimerfromtimingout. ifthe watchdogtimertimesout,itisanindicationthat the softwareisnolongerbeingexecutedintheintende d sequence.atthistimethewatchdogtimergenerates a resetsignaltothesystem. 21.1 wdt operations thewdtisenabledbysettingthewdtenableflag wdten ( misc[3] ).twotimesettings,2and8seconds, areselectablewithselectionbit wdtps ( misc[2] ).wdtis clockedbythe2hzclockfromthebasetimerandth erefore has0.5secondresolution.itisrecommendedthatt he watchdogtimerbeperiodicallyclearedbysoftware onceit isenabled.otherwise,softwareresetwillbegener ated whenthetimerreachedabinaryvalueof4or16. note:thewdtcanberesetbywritinganyvalue to misc register. afterasystemreset, wdten iscleared.thenthe wdtreturnstobeidle. table 21-1 system miscellaneous register (misc) address name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 def ault r wdten wdtps test test 0000 $038 misc w resetwdt bit2: wdtps : wdttimeouttimeselectionbit 0 =8seconds 1=2seconds bit3: wdten : wdtcontrolbit 0 =disablewdt 1=enablewdt bit1~0: test : thesetwobitsshouldbebothzeroinnormalopera tion
ST2202A ver2.5 63 / 75 9/16/2008 2 2 2 2 . . l l o o w w v v o o l l t t a a g g e e d d e e t t e e c c t t o o r r st2202hasabuiltinlowvoltagedetectorforpowe r management.thetypicalactivelevelofvoltagedet ectionis 2.6v.when lvden ( sys[0] )isset,detectorcircuitis enabledandthedetectionresultwillbeoutputted atthe samebitafter3 s.usingreadinstructiontwicecangetthis result:firstreadwillenableinitialstablenessc ontrol. secondreadequal'0'represents'lowvoltage'.onc elow voltagedetectorisenabled,itkeepsonconsuming power. soitisimportantthatremembertowrite0tolv detto disablethedetectorafterdetectioniscompleted. one sampleprogramisshownbelow: start: smb0 ST2202A ver2.5 64 / 75 9/16/2008 table 22-1 system control register (sys) address name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default r xsel ostp xstp wskp wait irren high 00000001 $030 sys w xsel ostp xstp wskp wait irren lvden 00000000 bit0: lvden :lowvoltagedetectorcontrolbit(w) 0 =disabledetector 1=enabledetector bit0: high :lowvoltagedetectorresult(r) 0=voltageislow 1 =voltageisnormal
ST2202A ver2.5 65 / 75 9/16/2008 2 2 3 3 . . e e l l e e c c t t r r i i c c a a l l c c h h a a r r a a c c t t e e r r i i s s t t i i c c s s 23.1 absolute maximum rations dcsupplyvoltage 0.3vto+6v operatingambienttemperature 10 cto+60 c storagetemperature 10 cto+125 c 23.2 dc electrical characteristics standardoperationconditions:vcc =3.0v,gnd=0v,t a =25 c,osc=2mhz,unlessotherwisespecified parameter symbol min. typ. max. unit condition operatingvoltage vcc 2.4 5.5 v operatingfrequency f 1 3.0 mhz vcc=2.4v~5.5v operatingfrequency f 2 4.0 mhz vcc=2.7~5.5v operatingcurrent i op 770 1100 a alli/oportareinputandpullup,executenop instruction,lcdcon standbycurrent i sb0 210 330 a alli/oportareinputandpull up,oscxon,lcdcon (wait0mode) cp=2mhz standbycurrent i sb1 1.2 a alli/oportareinputandpullup,oscx on,lcdcoff (wait1mode) inputhighvoltage v ih 0.7vcc vcc+0.3 v porta/b/c/d/e/l 0.85vcc v reset inputlowvoltage v il gnd0.3 0.3vcc v porta/b/c/d/e/l 0.15vccc v reset pullupresistance r i h 240 245 250 k porta/b/c/d/e/l(inputvoltage=0.7vcc) outputhighvoltage v oh 1 0.7vcc v porta/b/c/d/l (ioh=3.5ma) outputhighvoltage v oh 1 0.7vcc v portb (i oh =5.5ma) outputlowvoltage v ol 1 0.3vcc v porta/b/c/d/e/l(iol=7.5ma) outputhighvoltage v oh 2 0.7vcc v psg/dac,i oh =30ma. outputlowvoltage v ol 2 0.3vcc v psg/dac,i ol =70ma. lowvoltagedetector activelevel v lvd 2.4 2.55 2.7 v lowvoltagedetector current i lvdet 127 ua *notice: stressesabovethoselistedunder"absolutemaximum ratings"maycausepermanentdamagetothedevice. allthe ranges are stress ratings only. functional operatio n of this deviceattheseoranyotherconditionsabovethose indicated intheoperationalsectionsofthisspecificationi snotimpliedor intended.exposedtotheabsolutemaximumratingco nditions forextendedperiodsmayaffectdevicereliability.
ST2202A ver2.5 66 / 75 9/16/2008 23.3 ac electrical characteristics figure 23-1 external read timing diagram figure 23-2 external write timing diagram table 23-1 timing parameters for figure 23-1 and figure 23-2 standardoperationconditions:vcc =3.0v,gnd=0v,t a =25 c rating symbol characteristic min. typ. max. unit tsa addresssetuptime 10 ns tha addressholdtime 0 ns twlc cslpulsewidth 166 ns tclwl csassertedto r w asserted 1/2twlc ns twhch csnegatedafter r w isnegated 10 ns tcldh csassertedtodataoutputshigh 10 ns tsdw csassertedtodataoutisvalid 1/2twlc ns thdw dataoutholdtimeafter r w isnegated 20 ns tclrl csassertedto d r asserted 1/2twlc ns trhch csnegatedafter d r isnegated 10 ns tsdr datainvalidbefore d r isnegated 30 ns thdr datainholdtimeafter d r isnegated 10 ns tr signalrisetime 20 ns tf signalfalltime 10 ns
ST2202A ver2.5 67 / 75 9/16/2008 2 2 4 4 . . a a p p p p l l i i c c a a t t i i o o n n c c i i r r c c u u i i t t s s note: 1.thecapacitorconnectedto reset shouldbeofthevaluenotgreaterthan 0.01uf. 2.theresistorinparallelwiththeresetcapacito rhelpsalottogeneratecorrect resetsignalandshouldnotberemoved.thedrawbac kisanadditional currentofabout1.5uarises. 3.connect oe signalofanexternalromto rd ofst2202insteadofgnd topreventconflictofdatabuswhensoftwareerror ofwritingtoromoccurs.
ST2202A ver2.5 68 / 75 9/16/2008 2 2 5 5 . . q q f f p p 1 1 2 2 8 8 p p a a c c k k a a g g e e i i n n f f o o r r m m a a t t i i o o n n
ST2202A ver2.5 69 / 75 9/16/2008
ST2202A ver2.5 70 / 75 9/16/2008
ST2202A ver2.5 71 / 75 9/16/2008
romcodechecklist ver2.5 72 / 75 9/16/2008 ST2202A- 8-bit microcontroller with 256k bytes rom oscillator 32768hzcrystal rosc mhz(resistor= k ) resonator crystal mhz 2.4v~3.6v 3.0v 10% 3.3v 10% 3.6v~5.5v otherrange ~ v operating voltage note : maximumoperatingfrequency= 4.0 mhz@2.7v , 3.0 mhz@2.4v battery cr20 x aax aaax power down modes wai0 wai1 low voltage detector ? enabled ? disabled uart ? enabled,baudrate: bps ? disabled spi ? enabled,bitrate: bps ? disabled resolution: x duty:1/ bias:1/ vlcd: v driver: ? st8012x ? st2101cx ? st25 x ? lcd specifications note : theoptimalbiasis: 1 duty bias + = data sheet st2202usersmanualver code file: .bin date(y/m/d): 20 / / check sum: ???? h (bytemode) note:a.fileformatmustbebinaryandtheextensi onshouldbe.bin b.fileshouldbewrappedinzipformatfortransfe rringoremailing. c.onlysinglefileisallowed. d.filelengthis256kbytes. e.functionsshouldbecheckedontheemulationboa rdorbyrealchip. f.electriccharacteristicsoftheemulationboard arenotidenticalwiththoseofthereal chip. customer company signature sitronix fae/sa salse
romcodechecklist ver2.5 73 / 75 9/16/2008 project name date: item check note 1. checktheresistorofroscmatchesthedesiredfre quencyandvcc 2. checkandusetheupdatedversionofdatasheet 3. afterpoweron,enterwait1modefor1.5secondbe forenormaloperation 4. afterstartingoperation,switchoscxtonormalloa dmode 5. initializeuserramandeveryrelatedcontrolregis ter 6. confirmv op ,contrastlevel,duty,bias,framerate,alternati ngrateandthedisplay qualityoflcd 7. beforeenteringpowerdownmode,turnoffunusedpe ripheralsuchaslcd controller,psg,andlvd 8. confirmi/odirection,defaultstate,andfunction enablebits.enablepullupfor unusedinputpins 9. readfromaninputportafterthesignalsarestabl e.ex.whendoingkeyscan, delay12usfromanewscanvaluethenreadtheret urnlines. 10. ifaninputconnectstovccorgnddirectly,makes uretoremoveanydccurrent frominternalpullup/downresistorafterthestatu sisbeingread. 11. donotusebitinstructionstoregistersthatarer eadonly,writeonlyorhave differentfunctionsforreadandwrite. 12. disableunusedfunctionsandreservertiinstruct ionforunusedinterruptvectors 13. checkstackmemoryislimitedwithin256bytes. 14. designatestmodetocheckeverypossiblefunction 15. useast2202realchip,togetherwiththeemulation mode,todevelopmentthe wholesystem.testandverifyeverycondition 16. settingsofportlforlcdcontrolsignalsmustinc ludelinesbelow: : stz ST2202A theaboveinformationistheexclusiveintellectual propertyofsitronixtechnologycorp.andshallno tbedisclosed,distributedorreproduced withoutpermissionfromsitronix. sitronixtechnol ogycorp.reservestherighttochangethisdocumen twithoutpriornoticeandmakesno warrantyforanyerrorswhichmayappearinthisdo cument. sitronixproductsarenotintendedforuse inlifesupport,criticalcare,medical, safety equipment, or similar applications where pro ducts failure could result in injury, or loss of li fe, or personal or physical harm, or any militaryordefenseapplication,oranygovernmenta lprocurementtowhichspecialtermsorprovisions mayapply. ver2.5 74 / 75 9/16/2008 2 2 6 6 . . r r e e v v i i s s i i o o n n revision description page date 2.5 addchecklist. 70,71 2008/9/15 addwarmupprocessincrystalmode. 59 cancelthesys[4]oscxdrivingselection. 9,10,21,24,59, 61 2006/7/27 filllvdrange2.4v~2.7v. 62 addthenotethatkeepthenousedbit0 10 2.4 addpackageqfp128information. 66~69 2.3 modifypsgckfrequency. 22,36 2005/6/24 2.2 modifydcelectricalcharacteristics(wait0lcdon current) 62 2005/6/6 2.1 modify table186.addmoresettingsofdifferentbaudrat es. 54,55 2003/5/20 2.0 changeapplicationcircuitofconnectinganextern alrom addsection21.3acelectricalcharacteristics movepaddiagramanddeviceinformationtothefro nt 63 62 2003/5/5 1.9 removethecapacitorinparallelwiththeoscillat ionresistor. modifytypicalactiveleveloflowvoltagedetecto rtobe2.6v 60 58,59 2003/1/2 2003/4/2 1.8 modifyapplicationcircuitofsection22.seenote sbelowthefigure. 60 2002/11/20 fixerrorsonaddressesof brs and bdiv in table116 21 2002/11/4 modifytable166settingsforstandardbaudrates insection165 52 2002/11/13 1.7 forbidusingsramasthesourceofdmainsection 17 53 2002/11/13 modifyconnectionofxmdfromnctovccinsection 24 59 2002/9/25 switchdefinitionofpc4andpc5, pfc[4] and pfc[5] 2,3,7,43,44,45 2002/9/25 modifydefinitionof data_ready activelevelselectionbitin table 173 46 2002/9/25 1.6 modifydescriptionofoscillatormodeselectionin firstparagraph 18 2002/9/25 addoperationfrequencyrange 1,58 2002/9/4 1.5 addsection 16.2and 16.3 39,40 2002/9/4 modifydescriptionofpinxmd.connectionncis notallowed 3 2002/6/24 modifydescriptionofpinmmd/ cs0 and figure101.oneresistor shouldbeaddedbetweenvccandthispinwhenusing emulationmode. 3,16 2002/6/24 1.4 modifyselectionmethodofhighfrequencycrystal oscillatorfromcode optiontobondingoption 1 2002/6/24
ST2202A theaboveinformationistheexclusiveintellectual propertyofsitronixtechnologycorp.andshallno tbedisclosed,distributedorreproduced withoutpermissionfromsitronix. sitronixtechnol ogycorp.reservestherighttochangethisdocumen twithoutpriornoticeandmakesno warrantyforanyerrorswhichmayappearinthisdo cument. sitronixproductsarenotintendedforuse inlifesupport,criticalcare,medical, safety equipment, or similar applications where pro ducts failure could result in injury, or loss of li fe, or personal or physical harm, or any militaryordefenseapplication,oranygovernmenta lprocurementtowhichspecialtermsorprovisions mayapply. ver2.5 75 / 75 9/16/2008 adddescriptionofcontrolbit integ and table99 15 2002/6/24 changer/wabilityof lssal and lssah tobewriteonly 8,38,39 2002/6/24 modify table154dacsampleratedescription 34 2002/6/24 addchapter21:dccharacteristics 58 2002/9/4 modifydescriptionofpinmmd/ cs0 3,16 2002/6/12 1.3 addfiguresofconnectionofpinmmd/ cs0 16 2002/6/12 correctdescriptionofoutputlevelsof poff in table167 38 2002/6/05 addapplicationcircuit 55 2002/6/10 changenameoftest2pintommd,changenameofte st3pinto test2.modifydescriptionofmmd 3,15 2002/6/10 1.2 addsection 18.5settingsforstandardbaudrates 48 2002/6/1 0 modifybit0ofsystemcontrolregister sys 6,7,17,20,52,54 2002/4/20 addtwopinsxmdandtest3 2,3 2002/6/04 adddeviceinformationandpaddiagram 55,56 2002/6/04 changepsgoutputsnametopsgoandpsgob 2002/6 /04 1.1 modifylcdframerateequations141and142 38 2 002/6/04 1.0 secondrelease 2002/4/15

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